The Swatch Group Research and Development Ltd

The Swatch Research and Development Ltd.

Carlos Velasquez

Arnaud Casagrande

Emil Zellweger

Philippe Duc

Jean-Luc Arend

For the process for determining a distance, there is provided a succession of coded signals at high frequency transmitted between a base station and a wearable object. A preparation of a response signal is conducted in the wearable object on reception of the first synchronisation signal after activation of the wearable object. A transmission of successive coded signals at high frequency from the wearable object is conducted for the station, of which the last response signal is scrambled by a modulation of data on the last signal received at a high transfer rate from the station. An analysis is conducted in a processing unit of the base station after reception of the signals from the wearable object to accurately determine the distance separating the base station from the recognised wearable object.

Process and system for determining a distance between a wearable object and a base station

In the case of the process for secure access to a determined space, it is provided that after activation of the wearable object, a first coded signal is transmitted from the access or unlocking device, this first coded signal is received in the object and a coded response signal is transmitted with synchronization to the device after a defined time of transmission. A processing of the coded response signal converted in the processing unit of the device is conducted in order to check the defined time delay and the response code of the wearable object and to determine the flight times of the signals between the device and the wearable object. The distance separating the wearable object and the access or unlocking device is thus calculated to authorize access to the determined space if the calculated distance is below a determined threshold after recognition of the wearable object.

Process and system for secure access to a determined space by means of a wearable object

The signal receiver has means to suppress at least one higher harmonic component from a MEMS or crystal oscillator having a reference resonator in filtered intermediate signals of a signal receiver. The signal receiver comprises an antenna for receiving electromagnetic signals, a low noise amplifier for amplifying signals received by the antenna, one MEMS or crystal oscillator comprising a reference resonator to generate an oscillating signal with a predefined duty-cycle, a mixer for mixing the amplified and received signals with the oscillating signal to generate intermediate signals, a band-pass filter to filter the intermediate signals, and a duty-cycle controller coupled to the MEMS or crystal oscillator and coupled to the output of the band-pass filter to analyze the spectrum of the filtered intermediate signals and to modify the duty-cycle of the oscillating signal in response to the spectrum analysis of the filtered intermediate signals.

Signal receiver with a duty-cycle controller

The receiver () for FSK modulation signals includes an antenna () for receiving modulated data or control signals, a low noise amplifier () for amplifying and filtering the signals picked up by the antenna, a local oscillator () with a quartz resonator () for supplying high frequency, in-phase signals (S), and high frequency, in-quadrature signals (S), first and second mixers () for mixing the high frequency, in-phase and in-quadrature signals with the filtered and amplified incoming signals, in order to generate intermediate signals (I, Q), and a filtering unit () for filtering the intermediate signals. The receiver can be configured to receive modulated data or control signals at low rate. The filtering unit supplies intermediate signals (I, Q) filtered in a polyphase filter () to a first demodulation stage in medium or high rate mode, or intermediate, baseband signals filtered in the polyphase filter, which is converted into two low-pass filters (), to a second demodulation stage in low rate mode.

FSK modulation signal receiver with high sensitivity in low rate mode

The receiver () is for receiving radio-synchronous signals for adjusting the time base of a timepiece. The receiver includes an antenna () for receiving radio-synchronous signals, a low noise amplifier (), connected to the antenna, a frequency conversion unit () for converting the frequency of the filtered and amplified incoming signals from the amplifier, and a processing unit () receiving data signals (data_out) from the conversion unit for adjusting the time base. The conversion unit includes a local oscillator stage () with a quartz () for supplying oscillating signals (Sm) at a determined frequency, a mixer unit () for mixing the incoming signals with the oscillating signals from the oscillator stage to generate intermediate signals (IF), a bandpass filter () for filtering the intermediate signals (IF), and a demodulator () receiving the filtered intermediate signals and supplying the data signals. The local oscillator stage is configured automatically by a control signal (Cm) from the processing unit to adapt the frequency of the oscillating signals (Sm) in accordance with the incoming radio-synchronous signal frequency, so that the intermediate signal (IF) frequency is within the frequency band of the bandpass filter.

Radio-synchronous signal receiver for adjusting a time base, and method for activating the receiver

The amplifier circuit () includes a differential pair of PMOS transistors at input (P, P), whose source receives a current from a current source (). The gate of the first transistor (P) of the pair defines a non-inverting input (X) and the gate of the second transistor (P) of the pair defines an inverting input (X). A drain of the first transistor (P) of the differential pair is connected to a diode connected NMOS transistor (N) of a first current mirror (N, N), and a drain of the second transistor (P) of the differential pair is connected to a diode connected NMOS transistor (N) of a second current mirror (N, N). A diode connected PMOS transistor (P) of a third current mirror is connected to the drain of a second NMOS transistor (N) of the second current mirror, while a drain of a second PMOS transistor (P) of the third current mirror is connected to the drain of a second NMOS transistor (N) of the first current mirror to define a first output (OUT), which is inverted by a reverser (N, P) to supply an inverted output signal (OUT) capable of varying rail to rail. A first complementary NMOS transistor (N) is connected in the form of a reverser with the first PMOS transistor (P) of the differential pair. A second complementary NMOS transistor (N) is connected in the form of a reverser with the second MOS transistor (P) of the differential pair.

Low phase noise amplifier circuit

The dual-modulus prescaler circuit () is devised to operate at a very high frequency. This circuit includes an assembly formed of two dynamic D-type flip flops (), and two NAND logic gates () arranged in negative feedback between the two flip flops. The two flip flops are clocked by an input clock signal (CK) to supply a divided output signal (OUT) whose frequency matches the input clock frequency divided by 2 or by 3 as a function of a division mode selection signal (divb) applied to the input of the first NAND logic gate (). One non-inverted output of the second flip flop is connected to one input of the first flip flop (). The first dynamic flip flop includes three active branches and supplies a single inverted output signal. A third flip flop () with three active branches receives an inverted mode selection signal (div) at input in order to supply the mode selection signal to the inverted output thereof, clocked by the non-inverted output signal of the second flip flop.

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Neuchatel, Switzerland

Carlos Velasquez