Intel Corporation

Carlos Ornelas

Siddhartha Chhabra

Men Long

Alpa T Narendra Trivedi

Edgar Borrayo

Uday R Savagaonkar

Ignacio Javier Alvarez

David Arditti Ilitzky

Paul H Dormitzer

Stanley Steve Kulick

Ramadass Nagarajan

Daniel S Lake

Patrick Mead

Victor Palacios Rivera

Yassir Mosleh

Miryam Lomeli Barajas

John Tell

Methods and apparatus relating to heterogeneous compute architecture hardware/software co-design for autonomous driving are described. In one embodiment, a heterogeneous compute architecture for autonomous driving systems (also interchangeably referred to herein as Heterogeneous Compute Architecture or 'HCA' for short) integrates scalable heterogeneous processors, flexible networking, benchmarking tools, etc. to enable (e.g., system-level) designers to perform hardware and software co-design. With HCA system engineers can rapidly architect, benchmark, and/or evolve vehicle system architectures for autonomous driving. Other embodiments are also disclosed and claimed.

Heterogeneous compute architecture hardware/software co-design for autonomous driving

Embodiments of the invention include a machine-readable medium having stored thereon instructions, which if performed by a machine causes the machine to perform a method that includes assigning an urgency of requests based on a priority level for incoming requests and associated entries in at least one priority queue, assigning an urgency delta for anti-starvation that indicates urgency promotion to prevent starvation for the incoming requests in the at least one priority queue, determining conflict information including whether an incoming request is dependent on any request already present in the at least one queue, determining all contending requests within the at least one priority queue during a cycle, and sending a selected contending request to a memory controller for accessing memory.

Urgency based reordering for priority order servicing of memory requests

Memory encryption engine (MEE) integration technologies are described. A MEE system may include a MEE interface and a MEE core. The MEE interface may receive a data from an arbiter, where the data is selected by the arbiter from data at memory link queues. The MEE interface may adjust a timing rate to send the data to match a timing of a MEE core. The MEE core may be coupled to the MEE interface and may receive the data from the MEE interface.

Memory encryption engine integration

Memory encryption engine (MEE) integration technologies are described. A processor can include a processor core and an arbiter of a MEE system coupled to the processor core. The arbiter can receive a first contending request from a first queue and a second contending request from a second queue. The arbiter can further select the first queue to communicate the first message to an MEE of the MEE system or the second queue to communicate the second message to the MEE in view of arbitration criteria. The arbiter can further communicate the selected first message or the selected second message to the MEE.

A processor is described that includes one or more processing cores. The processor includes a memory controller to interface with a system memory having a protected region and a non protected region. The processor includes a protection engine to protect against active and passive attacks. The processor includes an encryption/decryption engine to protect against passive attacks. The protection engine includes bridge circuitry coupled between the memory controller and the one or more processing cores. The bridge circuitry is also coupled to the protection engine and the encryption/decryption engine. The bridge circuitry is to route first requests directed to the protected region to the protection engine and to route second requests directed to the non protected region to the encryption/decryption engine.

Bridging circuitry between a memory controller and request agents in a system having multiple system memory protection schemes

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Guadalajara, Mexico

Carlos Ornelas