Siemens Aktiengesellschaft

Infineon Technologies Ag

Carlos Mazure-Espejo

Frank S Hintermaier

Walter Hartner

Gunther Schindler

Volker Weinrich

G&uuml;nther Schindler

Christine Dehm

Manfred Engelhardt

Georg Braun

Rainer Bruchhaus

Thomas R&ouml;hr

Wolfgang H&ouml;nlein

Christoph Zeller

Andrej Majdic

Heinz Honigschmid

A semiconductor memory configuration has a plurality of selection transistors. Each selection transistor is connected to a first electrode of a storage capacitor. A second electrode of the storage capacitor is connected to a common plate. The common plate is provided below the selection transistors in a semiconductor body. A method of fabricating a semiconductor memory configuration is also provided.

Integrated semiconductor memory configuration with a buried plate electrode and method for its fabrication

A process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.

Process for producing an integrated semiconductor memory configuration

Disclosed is a method for producing semiconductor elements including a metal layer ( ) configured on a semiconductor substrate ( ). The inventive method consists of the following steps: a silicon layer ( ) is deposited on a metal layer ( ); an etch mask is applied in order to structure the silicon layer (1%); the silicon layer is selectively etched ( ) using the etch mask ( ); and the metal layer ( ) is structured in an etching process using a selectively etched silicon layer ( ) as a hard mask.

Method of fabricating semiconductor components

A circuit includes a sensor delivering a charge, a capacitor non-volatilely storing the charge, and a read and reset circuit reading out the stored charge. The capacitor has further connection terminals connected to the read and reset circuit and in parallel with the sensor terminals, and a ferroelectric storage dielectric intermittently connected to the sensor. The sensor can be a photodiode, a phototransistor, a Hall sensor, or a thermoelement. A switch can be connected between one of the further terminals and one of the sensor terminals. Preferably, the switch is a transistor and a drive circuit drives it. The sensor and the capacitor are formed in a semiconductor body. During a storage procedure, time periods during which the switch is on are coordinated with the sensor and/or capacitor to keep an electrical field present between the further terminals below a maximum value at which the ferroelectric dielectric saturates.

Circuit with a sensor and non-volatile memory having a ferroelectric dielectric capacitor

A layer configuration includes a material layer and a diffusion barrier which blocks diffusing material components. The barrier is disposed in the vicinity of a layer boundary of the material layer and is formed predominantly in grain boundaries of the material layer. A process for producing a diffusion barrier is also provided.

Layer configuration with a material layer and a diffusion barrier which blocks diffusing material components and process for producing a diffusion barrier

The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.

Easy to manufacture integrated semiconductor memory configuration with platinum electrodes

Process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.

Process for producing barrier-free semiconductor memory configurations

A method for producing a memory configuration that comprises a multiplicity of memory cells, and has storage capacitors whose first electrodes are configured in plate form in a parallel manner one above the other. These electrodes are in electrical contact with selection transistors of the memory cell through contact plugs having different lengths. The first electrodes preferably extend beyond the cell area of one memory cell.

Method for the production of an integrated semiconductor memory configuration

A method for producing an integrated semiconductor memory configuration, in particular uses ferroelectric materials as storage dielectrics. A conductive connection between a first electrode of a storage capacitor and a selection transistor is produced only after deposition of the storage dielectric.

Method for producing barrier-free semiconductor memory configurations

A ceramic layer, in particular having ferroelectric, dielectric or superconducting properties, uses compounds with a simple structure as precursors and only methanoic acid, acetic acid or propionic acid and, where appropriate, water as solvent.

Process for producing a ceramic layer

A production process for a capacitor electrode formed of a platinum metal includes producing a conductive electrode body on a substrate having a silicon-containing surface for the capacitor electrode. Platinum is deposited over the full surface, the platinum is silicized in a temperature step outside the electrode body and the platinum silicide is removed. The advantage of the invention is the avoidance of an etching process for metallic platinum.

Production process for a capacitor electrode formed of a platinum metal

A process for producing a ceramic layer containing Bi, in particular having ferroelectric, dielectric or superconducting properties, includes using only an organic acid C.sub.n H.sub.2n+1 COOH wherein n=0, 1 or 2 and, where appropriate, water, as a solvent for the precursor containing Bi.

Process for producing a ceramic layer containing Bi

A barrier layer is formed on the contact plug of the semiconductor body. The barrier layer prevents oxidation of the contact plug. The barrier layer is produced by chemically reacting a prestructured metallic transition material with one or more reaction partners.

Method of producing a barrier layer in a semiconductor body

A memory configuration with a self-aligning non-integrated capacitor configuration includes a capacitor configuration and a transistor configuration which can be joined together in a self-aligning manner in such a way that each first contact of a transistor of the transistor configuration is connected to a respective second contact of a memory capacitor of the capacitor configuration. In order to align the two configurations, the second contacts are constructed in a protruding manner, and when joining takes place they engage in a structure including elevations.

Memory configuration with self-aligning non-integrated capacitor

An integrated memory includes a cell array having bit lines, word lines and writable memory cells. A first differential sense amplifier has connections connected to a data line pair through which the first sense amplifier reads information from one of the memory cells during a read access operation in order to amplify it subsequently, and through which the first sense amplifier writes information to one of the memory cells during a write access operation. The relevant information is transferred as differential signals through the data line pair and is temporarily stored by the first sense amplifier during every write access operation. The memory also has a switching unit through which the data line pair is connected to the connections of the first sense amplifier, for interchanging the lines of the data line pair in relation to the connections of the first sense amplifier, depending on the switching state of the switching unit. The switching state of the switching unit is changed at least once during a write access operation, so that the information to be written is written to the relevant memory cell by the first sense amplifier initially in noninverted form and then in inverted form. A method for preventing aging in a memory cell in an integrated memory is also provided.

Growing community of inventors

München, Germany

Carlos Mazure-Espejo