Intel Corporation

Carlos Madriles Gimeno

Fernando Latorre

Pedro Marcuello

Antonio Gonzalez

Grigorios Magklis

Pedro Lopez

Antonio González

Marc Lupon

Polychronis Xekalakis

Raul Martinez

Josep M Codina

Enric Gibert Codina

Daniel Ortega

Kyriakos A Stavrou

Demos Pavlou

Georgios Tournavitis

Mirem Hyuseinova

Christos E Kotselidis

Crispin Gomez Requena

Alejandro Martinez Vicente

Carlos García Quinones

Jesús Sánchez

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

Managed instruction cache prefetching

In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.

Enabling speculative state information in a cache coherency protocol

Growing community of inventors

Barcelona, Spain

Carlos Madriles Gimeno