Qualcomm Incorporated

Carlos Javier Moreira

Jason Edward Podaima

Kyle Ernewein

Paul Christopher John Wiercienski

Meghal Varia

Serag Gadelrab

Alexander Miretsky

Bohuslav Rychlik

Muhammad Umar Choudry

Serag Monier GadelRab

Paul Chow

Dhaval Kanubhai Patel

Simon Peter William Booth

Manokanthan Somasundaram

Ruolong Liu

Thomas David Dryburgh

According to various aspects, just-in-time system bandwidth changes may be implemented in hardware to optimize power consumption and performance in an electronic device. More particularly, in a periodic system associated with an electronic device, a bandwidth for a next frame may be configured during a current frame via software operating on the electronic device. Hardware associated with the periodic system may issue a bandwidth change request for the next frame when a current time reaches a bandwidth increase threshold in response to actual processing time associated with the current frame finishing prior to the bandwidth increase threshold, which may be defined relative to a timer deadline that defines when the next frame starts to process.

Just-in time system bandwidth changes

Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.

Speculative pre-fetch of translations for a memory management unit (MMU)

Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.

Providing memory management functionality using aggregated memory management units (MMUs)

Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.

Multi-threaded translation and transaction re-ordering for memory management units

Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media

Methods and systems for pre-fetching address translations in a memory management unit (MMU) of a device are disclosed. In an embodiment, the MMU receives a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, pre-fetches a translation of the instruction from a translation table in a memory of the device, and stores the translation of the instruction in a translation cache associated with the MMU.

Growing community of inventors

Markham, Canada

Carlos Javier Moreira