Taiwan Semiconductor Manufacturing Comp. Ltd.

Carlos Hernando Diaz

Chung-Cheng Wu

Bi-Ling Lin

Jyh-Haur Wang

Chih-Hao Wang

Kuo-Cheng Ching

Chung-Te Lin

Chao-Cheng Chen

Bao-Ru Young

Ryan Chia-Jen Chen

Kuo-Hua Pan

Yuan-Sheng Huang

Hsien-Chin Lin

Mu-Chi Chiang

Hui-Wen Lin

Ting-Hua Hsieh

Chih-Chiang Wang

Su-Yu Lu

Harry Hak-Lay Chuang

Kong-Bong Thei

Ming Zhu

A method of making a semiconductor device includes depositing a TiN layer over a substrate. The method further includes doping a first portion of the TiN layer using an oxygen-containing plasma treatment. The method further includes doping a second portion of the TiN layer using a nitrogen-containing plasma treatment, wherein the second portion of the TiN layer directly contacts the first portion of the TiN layer. The method further includes forming a first metal gate electrode over the first portion of the TiN layer. The method further includes forming a second metal gate electrode over the second portion of the TiN layer, wherein the first metal gate electrode has a different work function from the second metal gate electrode, and the second metal gate electrode directly contacts the first metal gate electrode.

Method of making gate structure of a semiconductor device

A method for forming FET devices with attenuated gate induced drain leakage current. There is provided a silicon semiconductor substrate employed within a microelectronics fabrication. There is formed within the silicon substrate field oxide (FOX) dielectric isolation regions defining an active silicon substrate device area. There is formed over the substrate a silicon oxide gate oxide insulation layer employing thermal oxidation. There is then formed over the silicon oxide gate oxide insulation layer a patterned polycrystalline silicon gate electrode layer. There is then thermally oxidized the substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and in the adjacent silicon substrate area. There is then etched back the thicker silicon oxide layer from the silicon substrate area adjacent to the gate electrode. There is then formed employing low energy ion implantation shallow junction source-drain extension regions adjacent to the gate electrode. There is then formed source-drain regions to complete the FET device, which exhibits attenuated drain leakage current. The present invention may be employed to fabricate complementary metal-oxide-silicon (CMOS) FET devices of either polarity with attenuated gate induced drain leakage (GIDL) current, short channel effect (SCE) and punch-through leakage current in integrated circuit microelectronics fabrications wherein low power drain is desired.

Method to reduce the gate induced drain leakage current in CMOS devices

A method of forming a pocket implant region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an indium pocket implant region, in the area of a P type semiconductor to be used to accommodate an N type source/drain region, an ion implantation procedure is used to place antimony ions in the indium pocket implant region. The presence of antimony ions limits the broadening of the indium pocket implant profile during subsequent anneal procedures, used to activate implanted ions. Formation of an implanted, lightly doped, N type source/drain region, insulator spacers on the sides of a gate structure, and formation of a heavily doped, N type, source/drain region, complete the process sequence used to form the NMOS, transfer gate transistor.

Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect

A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain extensions are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.

Ultra-shallow junction formation by novel process sequence for PMOSFET

A method for forming within a substrate employed within a microelectronics fabrication a field effect transistor with attenuated drain leakage current. There is provided a silicon substrate within which are fabricated nMOS field effect transistors (FET) with lightly-doped n-type drain regions (nLDD) employing arsenic (As) dopant. There is then implanted indium (In) dopant atoms adjacent to the As diffused junction to form a p-type pocket therein. There is then avoided the customary high temperature rapid thermal annealing (RTA) step and instead employed a thermal annealing for 2 hours at 750 degrees centigrade, whereupon the implanted indium atom undergo transient enhanced diffusion (TED) to form a graded junction profile, resulting in attenuated drain leakage current and no increased reverse short channel effect from the strong segregation of indium into silicon oxide.

Drain leakage reduction by indium transient enchanced diffusion (TED) for low power applications

A method is disclosed to form a shallow trench isolation (STI) having reduced junction leakage by avoiding undercutting near the shoulder of the trench. This is accomplished by using the pad oxide as a screen oxide and not removing it by wet dip etch as is normally practiced. Instead, an extra layer of low temperature oxide is added through thermal growth, and then the resulting composite is removed together with minimal undercutting at the shoulder corners of the trench. Subsequently, gate oxide is grown thermally to complete the forming of the STI.

Formation of shallow trench isolation (STI)

Growing community of inventors

Hsin-Chu, Taiwan

Carlos Hernando Diaz