Taiwan Semiconductor Manufacturing Comp. Ltd.

Texas Instruments Corporation

Hewlett-packard Company

University of Illinois

Carlos H Diaz

Jean-Pierre Colinge

Chih-Hao Wang

Kuo-Cheng Ching

Ta-Pen Guo

Ying-Keung Leung

Ling-Yen Yeh

Zhiqiang Wu

Chih-Sheng Chang

Chun-Hsiung Lin

Cheng-Yi Peng

Chun-Chieh Lu

Wai-Yi Lien

Ching-Wei Tsai

Chung-Cheng Wu

Yee-Chia Yeo

Tzu-Chiang Chen

Wen-Hsing Hsieh

Tung-Ying Lee

Yi-Ming Sheu

Chia-Hao Chang

I-Sheng Chen

Gwan Sin Chang

Ken-Ichi Goto

Meng-Hsuan Hsiao

Shau-Lin Shue

Kuo-Cheng Chiang

Syun-Ming Jang Jang

Shi Ning Ju

Yih Wang

Ka-Hing Fung

Wilman Tsai

Chien-Hsun Wang

Yu-Ming Lin

Harry-Hak-Lay Chuang

Chao-Cheng Chen

Bao-Ru Young

Fu-Liang Yang

Cheng-Hsien Wu

Ryan Chia-Jen Chen

Ming Zhu

Chao-Ching Cheng

Mao-Lin Huang

Charvaka Duvvury

Harry Hak-Lay Chuang

Chia-Cheng Ho

Yi-Hsiung Lin

Yuan-Sheng Huang

Hsin-Ping Chen

Chung-Ju Lee

Tien-I Bao

Gerben Doornbos

Kuan-Ting Pan

Tai-I Yang

Mark Van Dal

Wen-Chin Lee

Ru-Liang Lee

Da-Wen Lin

Yu-Chao Lin

Yu-Sheng Chen

Tsung-Hsing Yu

Tzer-Min Shen

Hua Feng Chen

Mahmut Sinangil

Krishna Kumar Bhuwalka

Huicheng Chang

Chun Hsiung Tsai

Hung-Li Chiang

Chenming Hu

Hun-Jan Tao

Shy-Jay Lin

Jonathan Tsung-Yung Chang

Yue-Der Chih

Shao-Ming Yu

Matthias Passlack

Wei-Hao Wu

Martin Christopher Holland

Hsi-Wen Tien

Cheng-Hsiung Tsai

Yung-Hsu Wu

Jau-Yi Wu

Jin-Aun Ng

Hsien-Wei Chen

Shin-Puu Jeng

Hao-Yi Tsai

Kong-Beng Thei

Tien-Lu Lin

Shi-Ning Ju

Cheng-Tung Lin

Wei-Jung Lin

Kuo-Tai Huang

Hung-Der Su

Chien-Hua Huang

Yu Chao Lin

Hsin-Chieh Yao

Chien-Chao Huang

Kai-Chieh Yang

Yung-Chih Wang

Sheng-Chen Chung

Peng-Fu Hsu

In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

Semiconductor device and manufacturing method thereof

A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Contacts for highly scaled transistors

A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, a gate conductive structure over the gate dielectric layer, and a first insulating spacer alongside the gate conductive structure and over the plurality of nanostructures. The first insulating spacer is in direct contact with the gate conductive structure and the gate dielectric layer.

Multi-gate semiconductor device and method for forming the same

Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

Series of parallel sensing operations for multi-level cells

A semiconductor device including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes a transistor, wherein the transistor has a source region and a drain region. The interconnect structure is disposed over the semiconductor substrate, wherein the interconnect structure includes a plurality of interlayer dielectric layers, a first via and a memory cell. The plurality of interlayer dielectric layers are over the semiconductor substrate. The first via is embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor. The memory cell is disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via.

Memory device, semiconductor device, and method of fabricating semiconductor device

A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

Nanowire stack GAA device with inner spacer and methods for producing the same

Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.

Memory cell and semiconductor device having the same

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Devices having a semiconductor material that is semimetal in bulk and methods of forming the same

A memory cell includes a bottom electrode, a storage element layer, a first buffer layer, and a top electrode. The storage element layer is disposed over the bottom electrode. The first buffer layer is interposed between the storage element layer and the bottom electrode, where a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer. The top electrode is disposed over the storage element layer, where the storage element layer is disposed between the top electrode and the first buffer layer.

Memory cell, semiconductor device having the same, and methods of manufacturing the same

According to another embodiment, a method of forming a transistor is provided. The method includes the following operations: providing a substrate; providing a source over the substrate; providing a channel connected to the source; providing a drain connected to the channel; providing a gate insulator adjacent to the channel; providing a gate adjacent to the gate insulator; providing a first interlayer dielectric between the source and the gate; and providing a second interlayer dielectric between the drain and the gate, wherein at least one of the formation of the source, the drain, and the channel includes about 20-95 atomic percent of Sn.

Method of forming transistor

A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.

Multi-gate device and method of fabrication thereof

In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

Method for forming integrated semiconductor device with 2D material layer

A semiconductor structure includes a substrate, a first epitaxial layer, a second epitaxial layer, and a transistor. The substrate includes a first pyramid protrusion, a second pyramid protrusion, a third pyramid protrusion, and a fourth pyramid protrusion. The first and second pyramid protrusions are arranged along a first direction, the second and fourth pyramid protrusions are arranged along the first direction, and the first and third pyramid protrusions are arranged along a second direction crossing the first direction. The first epitaxial layer is over the substrate and in contact with the first, second, third, and fourth pyramid protrusions. The second epitaxial layer is over the first epitaxial layer. The transistor is over the second epitaxial layer.

Heterogeneous semiconductor device substrates with high quality epitaxy

Growing community of inventors

Mountain View, CA, United States of America

Carlos H Diaz