Applied Materials, Inc.

Carlos Caballero

Qintao Zhang

Samphy Hong

David Jon Lee

Lei Zhong

Felix Levitov

Kazuyoshi Iwama

Peichun Lv

Taisen Kawahiro

Durgaprasad Chaturvedula

Ramakrishnan Bashyam

A method of forming a gate of a planar metal oxide semiconductor field effect transistor (MOSFET) reduces gate-drain capacitance. The method may include forming a first gate dielectric portion of the planar MOSFET with a first thickness that is configured to reduce the gate-drain capacitance of the planar MOSFET, forming a second gate dielectric portion of the planar MOSFET on the substrate with a second thickness less than the first thickness, and forming the gate of the planar MOSFET on the first gate dielectric portion and the second gate dielectric portion on the substrate.

Methods for forming planar metal-oxide-semiconductor field-effect transistors

Methods and apparatuses for filling an epitaxial layer into a trench/via/structure formed in a substrate with good deposition profile control and film uniformity across the substrate are provided. In one embodiment, a method of depositing a epitaxial layer on the substrate includes supplying a gas mixture having a first ratio of a dichlorosilane gas to a chlorine containing gas into the processing chamber, altering the gas mixture to have a second ratio of the dichlorosilane gas to the chlorine containing gas into the processing chamber, maintaining a substrate temperature of between about 600 degrees Celsius and about 1000 degrees Celsius, and filling an opening formed in a substrate.

Process of selective epitaxial growth for void free gap fill

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Covina, CA, United States of America

Carlos Caballero