Nxp B.v.

Carlos Basto

Jan-Willem Van De Waerdt

A method of producing an integrated circuit () using a system-on-chip (SoC) architecture includes providing a first circuit () in a first island of synchronicity (IoS); and providing a source-synchronous data link () between the first circuit () in the first IoS and a hard core () in a second IoS for communicating n-bit data elements between the first circuit () and the hard core (). The source-synchronous data link () includes a set of n data lines () for transporting the n-bit data elements between the first circuit () and the hard core (), and a source-synchronous clock line () for transporting a source clock between the first circuit () and the hard core () for clocking the n-bit data elements. The hard core () does not include a bus interface adaptor for interfacing with the source-synchronous data link ().

Source-synchronous data link for system-on-chip design

A cache memory system and method for supporting multiple simultaneous store operations using a plurality of tag memories is provided. The cache data system further provides a plurality of multiple simultaneous cache store functions along with a single cache load function that is simultaneous with the store functions. Embodiments create a cache memory wherein the cache write buffer does not operate as a bottle neck for data store operations into a cache memory system or device.

Growing community of inventors

Santa Clara, CA, United States of America

Carlos Basto