Motorola Corporation

Freescale Semiconductor,inc.

Carlos A Greaves

Michael R May

Hector Adrian Sanchez

Xinghai Tang

Jim P Nissen

Mathew A Rybicki

Jose Melanio Nunez

Thang Q Nguyen

Harold M Martin

Perry H Pelley

Alan Lee Westwick

James G Gay

Matthew A Pendleton

Howard E Levin

Luis A Bonet

Peter R Molnar

Jose G Corleto

Terence L Johnson

Mauricio A Zavaleta

Sujit Sudhaman

Jeffrey P Gleason

Jody H Everett

Perry H Pelly

John M Porter

Robin Wiprud

A method and circuit includes providing at least one conductor for receiving an input signal. A termination circuit and a clamp circuit are coupled to the at least one conductor. The termination circuit is enabled while the clamp circuit remains enabled. The clamp circuit is disabled. After disabling the clamp circuit, while the termination circuit remains enabled, both a first differential comparator and a second differential comparator are enabled. The first differential comparator receives a first differential input signal at a first input and a second differential input signal at a second input. The second differential comparator detects when a difference between the first differential input signal and the second differential input signal is greater than a predetermined value and enables transfer of an output of the first differential comparator to a memory controller.

Circuit for controlling data communication with synchronous storage circuitry and method of operation

Hashing and pattern matching are used in an information processing system to process incoming messages from a network such as an Ethernet-based network. Using hashing and pattern matching increases the efficiency of message acceptance and rejection without increasing software-based processor tasks. A hash function and a pattern matching function are performed on a message received by an information processing system, and the message is selectively accepted based on at least one of a hash result and a pattern matching result. The incoming message can be searched for the existence of patterns and the absence of the patterns. The incoming message can be searched for the existence of multiple patterns. The results of pattern matching can be used not only for acceptance and rejection of messages, but also for other post-receipt tasks such as selective storage of incoming messages according to identified relative priorities or absolute criticality of messages having particular pattern matches.

Network message filtering using hashing and pattern matching

A memory () has a plurality of memory cells, a serial address port () for receiving a low voltage high frequency differential address signal, and a serial input/output data port () for receiving a high frequency low voltage differential data signal. The memory () can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array () by interleaving in multiple sub-arrays (). During a hidden refresh mode of operation, one sub-array () is accessed while another sub-array () is refreshed. Two or more of the memories () may be chained together to provide a high speed low power memory system.

Memory with serial input-output terminals for address and data and method therefor

A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to opposite states within a second voltage range between third and fourth supply voltages in response to switching of the first and second nodes. The protection layer couples the first and second nodes to third and fourth nodes via respective first and second isolation paths. The isolation paths operate to keep the first and second nodes within the first voltage range and to keep the third and fourth nodes within the second voltage range. Isolation enables the use of thin gate-oxide devices for speed while extending the voltage range beyond the maximum voltage allowable for a single thin gate-oxide device.

Cascadable level shifter cell

Network message processing using inverse pattern matching

A memory () has a plurality of memory cells, a transceiver () for receiving a low voltage high frequency differential address signal, and a serial input/output data port () for receiving a high frequency low voltage differential data signal. The memory () can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is scored in the memory array () by interleaving in multiple sub-arrays (). During a hidden refresh mode of operation, one sub-array () is accessed while another sub-array () is refreshed. Two or more of the memories () may be chained together to provide a high speed low power memory system.

Memory with serial input/output terminals for address and data and method therefor

A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a state of the first preliminary drive signal AC coupled to the first signal, first and second drive circuits receiving the preliminary drive signals and providing first and second drive signals, where the first drive circuit operates within a second voltage range having a greater common mode voltage and where the second drive circuit operates within a third voltage range, and an output that switches an output node within a voltage range that is greater than a maximum voltage range. The first, second and third voltage ranges are each within the maximum voltage range suitable for thin-gate devices.

High speed output buffer with AC-coupled level shift and DC level detection and correction

A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

Fully programmable phase locked loop

A transceiver (5) for an asymmetric communication system such as asymmetric digital subscriber line (ADSL) includes a configuration register (71) defining operation at either a central office (CO) or a remote terminal (RT). The configuration register (71) includes a control bit (72) for selecting either CO or RT mode. The transceiver (5) includes a signal processing module (70) configured according to the state of the control bit (72). For example, a digital interface (70) converts transmit data into transmit symbols and converts received symbols into receive data. The digital interface (70) uses a large memory (158) as a buffer in the transmit path and a small memory (160) as a buffer in the receive path in CO mode. In RT mode, the digital interface (70) uses the small memory (160) in the transmit path and the large memory (158) in the receive path. The selective configuration allows a single integrated circuit to be used in both CO and RT equipment.

Single-chip software configurable transceiver for asymmetric

A cascaded integrator-comb (CIC) interpolation filter is included within a digital-to-analog converter (138) and includes two up-samplers (150, 164). The two up-samplers (150, 164) also include a sample-and-hold function. The first up-sampler (150) up-samples an output of a differentiator (140). The second up-sampler (164) up-samples an output of an integrator (152) This reduces the area and power requirements of the CIC interpolation filter, while providing approximately the same filtering performance in the pass band and transition band. The total over-sample ratio of the CIC interpolation filter is equal to the first up-sampling ratio multiplied by the second up-sampling ratio. The stop band requirements of the CIC interpolation filter determines the relative sizes of the first and second up-sampling ratios.

Cascaded integrator-comb interpolation filter

A data stream to be transmitted is received by a digital interface (52) and converted into a frequency encoded data. A gains block (54) receives the frequency encoded data and a gain adjustment signal, and produces a gain adjusted data to compensate for undesirable system level passband gain variation. The gain adjusted data is converted to a time domain data. The time domain data is processed by a high-pass and a droop correction filter (58, 59) to produce a filtered data. The filtered data is provided through an analog front-end (60) in order to provide a filtered analog data.

Method and apparatus for frequency domain ripple compensation for a

A dual tone detector (100) for a single dual tone, a dual tone multi-frequency (DTMF), or similar system processes an input signal through both bandpass (103) and band reject (104) tone detectors. If both the bandpass (103) and band reject (104) tone detectors detect a tone, then the dual tone detector (100) provides a tone detect output signal. If only the bandpass tone detector (103), which is susceptible to false tones, detects a tone, then a voice input signal is muted and the tone detector (100) activates the tone detect output signal only if both the bandpass (103) and band reject (104) tone detectors subsequently detect a tone. In one embodiment, a dual bandpass/band reject tone detector (120) processes the input signal through shared front-end band reject filters (121, 122), limiters (124), resonators (127, 128), and a processing section (130) in order to save circuit area. Limiter and peak detector functions are also implemented in shared circuitry to further reduce circuit area.

Dual tone detector operable in the presence of speech or background

A signal processor such as an ADPCM decoder (128b) receives an input signal. As part of the CCITT Recommendation G.726 algorithm, an inverse adaptive quantizer (41) processes the input signal to provide a quantized difference signal d.sub.q (k). When enabled, a noise detector (50) samples signal d.sub.q (k) once for each of a predetermined number of received samples. The noise detector (50) adds the absolute value of signal d.sub.q (k) to a total energy estimate. At the end of the predetermined number of samples, the noise detector (50) compares the total energy estimate to a product of a noise threshold and the predetermined number. If the total energy estimate exceeds this product, then a noise indication is provided. In another embodiment (228b) a noise detector (250) compares an existing energy estimate signal d.sub.ml (k) computed by an adaptation speed control block (48) as part of the G.726 algorithm to an energy threshold to save processing time.

Method and apparatus for noise burst detection in a signal processor

A bandgap voltage reference circuit (50, 100) which operates at low power supply voltages provides a reference current as either a one- or a two-.DELTA.V.sub.BE voltage across a first resistor (82, 133). A current proportional to the reference current is mirrored into one terminal of a second resistor (94, 133) to provide the bandgap voltage. Compensation for base currents injected into the circuit (50, 100) by two transistors forming the .DELTA.V.sub.BE reference is provided. In one embodiment (50), base currents of first (66) and second (87) transistors which have equal emitter areas and collector current density as the two transistors (68, 85) forming the .DELTA.V.sub.BE reference compensate for the injected base currents. In another embodiment (100), a single transistor (127) injects current substantially equal to the sum of the base currents of the two transistors (116, 121) forming the .DELTA.V.sub.BE reference. The single transistor (127) has twice the emitter area of one of the transistors (116) forming the .DELTA.V.sub.BE reference.

Bandgap voltage reference circuit

A low voltage precision current generator includes an amplifier, a first transistor, a current portion, and an output portion. The amplifier has first and second input terminals and changes an output voltage until voltages at the first and second input terminals are equal. An input voltage which may be a stable reference voltage or a variable voltage is received at the first input terminal. The second input terminal is connected to the current portion in order to provide a reference current proportional to a voltage difference between the voltage at the second input terminal and a power supply voltage. The amplifier controls the conductivity of the first transistor in order to regulate the voltage at its second input terminal. A precision current precision current proportional to the reference current is then provided.

Growing community of inventors

Austin, TX, United States of America

Carlos A Greaves