Advanced Micro Devices Corporation

Hart Intercivic, Inc.

Carlos A Gomez

James M Canter

Steven Joel Blachman

A local electronic voting network configured as a daisy chain network is provided. Each network device may include a switch for routing and propagating voting network communications. A TCP/IP protocol over Ethernet based connections may be used. Voting devices may include a relay configured such that in case of power down of a voting device the relay shunts the communications down the network. Multiple input/output ports may be provided on network devices and a physical port blocker is provided to block unused ports. A network controller may include a display screen which utilizes a graphical user interface to display status information regarding individual ones of the voting devices that are coupled to the voting network.

System and method for electronic voting network

Device leads on a packaged integrated circuit are protected during a decapsulation process. A composite material such as wax is applied to coat the leads. At least a portion of a package containing the integrated circuit is then removed while the composite material is coating the leads, the coated leads being protected from fumes associated with the decapsulation process and less susceptible to deformation during handling. The composite material is then removed from the leads after the portion of the package is removed from the packaged device.

Method of protecting device leads of a packaged integrated circuit

A system for interfacing wafer sort prober apparatus and packaged IC handler apparatus to a common test computer is provided that includes a single motherboard and at least one daughter board. The motherboard includes a probe card interface area having a plurality of contactors that mate with symmetrical connectors provided on a probe card. The probe card includes a series of contact probes adapted to make electrical connection to a semiconductor wafer. The motherboard also includes a hole in its center to allow visual inspection and alignment of the wafer when it is positioned beneath the motherboard. A test head interface area is also provided on the motherboard and includes a plurality of contactors that mate with symmetrical contactors provided on a test head assembly of the test computer. The motherboard further includes a daughter board interface area having a plurality of contactors that mate with symmetrical contactors provided on each daughter board. A connector is provided on each daughter board that mates with an IC contactor unit. As a result, a common interface board can be used during both wafer sort testing and packaged IC testing. Cost is thereby reduced since entirely separate boards are not required. The motherboard incorporates interconnecting lines and support interface circuitry common to both wafer sort and packaged IC testing. In addition, by using a packaged IC standard unit (that is, an IC that is known to be completely functional), debugging of the motherboard interconnecting lines and support circuity for the wafer sort configuration is simplified. Debugging of the wafer sort configuration is simplified since the daughter board can be attached directly to the motherboard independent of a prober apparatus, and thus mechanical access to the motherboard is not obstructed.

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Austin, TX, United States of America

Carlos A Gomez