Tokyo Electron Limited

Carlos A Fonseca

Mark H Somervell

Steven A Scheer

Wallace Paul Printz

Nathan Ip

Anton J deVillers

Jeffrey Smith

Michael Carcasi

Benjamen M Rathsack

Lior Huli

Joel Estrella

Joshua Hooge

Teruhiko Kodama

Jun Shinagawa

Roel Gronheid

Toshihiro Kitao

Megan Wooley

Sophie Bernard

Aspects of the disclosure provide a method for wafer result prediction. The method includes determining predictor parameters of a semiconductor process using domain knowledge that includes knowledge of the semiconductor process, a processing tool associated with the semiconductor process, a metrology tool, and/or the wafer. The method also includes removing collinearity among the predictor parameters to obtain key predictor parameters, and selecting a subset of the key predictor parameters based on metrology data of the wafer obtained from the metrology tool. The method further includes building a virtual metrology (VM) model on the subset of the key predictor parameters and may include predicting wafer results using the VM model.

Virtual metrology for wafer result prediction

Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Enhancement of yield of functional microelectronic devices

In one embodiment, a method includes obtaining wafer measurements of a characteristic of a semiconductor wafer at each of a plurality of process steps during a semiconductor wafer fabrication process, where each of the wafer measurements is associated with a spatial location on the semiconductor wafer from which the measurement is obtained. The method may further include creating a process step fingerprint from the obtained wafer measurements for each process step. The method may further include correlating the process step fingerprint of one of the plurality of process steps to the process step fingerprint of another one of the plurality of process steps to produce a transfer function.

Systems and methods for manufacturing microelectronic devices

Methods and systems for PS-CAR photoresist simulation are described. In an embodiment, a method includes calibrating initial conditions for a simulation of at least one process parameter of a lithography process using a radiation-sensitive material. In such an embodiment, the radiation-sensitive material includes a first light wavelength activation threshold that controls the generation of acid to a first acid concentration in the radiation-sensitive material and controls generation of photosensitizer molecules in the radiation-sensitive material, and a second light wavelength activation threshold that can excite the photosensitizer molecules in the radiation-sensitive material that results in the acid comprising a second acid concentration that is greater than the first acid concentration, the second light wavelength being different from the first light wavelength. Further, the method may include performing a lithography process using the previously-determined at least one process parameter.

Photo-sensitized chemically amplified resist (PS-CAR) model calibration

A method and apparatus are disclosed for optimizing a rinsing and drying process in semiconductor manufacturing. The optimization seeks to maximize processing throughput while maintaining low defect counts and high device yields, and utilizes simulation and experimental data to set the optimal process parameters for the rinsing and drying process. Improved methods of rinse liquid and purge gas nozzle movement are also disclosed.

Method and apparatus for substrate rinsing and drying

Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

Substrate backside texturing

A method and system for patterning a substrate using a lithographic process, such as a dual tone development process, is described. The method comprises use of at least one photo-activated acid enhancement component to improve process latitude for the dual tone development process.

Dual tone development with a photo-activated acid enhancement component in lithographic applications

A method and system for patterning a substrate using a dual tone development process is described. The method and system comprise a flood exposure of the substrate to improve process latitude for the dual tone development process.

Flood exposure process for dual tone development in lithographic applications

A method of patterning a substrate using a dual-tone development process is described. The patterning method comprises forming a layer of radiation-sensitive material on a substrate, wherein the layer of radiation-sensitive material comprises a dual tone resist. Thereafter, the patterning method comprises performing one or more exposures of the layer of radiation-sensitive material to one or more patterns of radiation, wherein at least one of the one or more exposures comprises using a mask having a dual-tone mask pattern region configured for printing dual tone features and a half-tone mask pattern region configured for printing half-tone features. Furthermore, the half-tone mask pattern region is optimized for use with the dual tone resist.

Method for creating gray-scale features for dual tone development processes

A method for patterning a substrate is described. In particular, the invention relates to a method for double patterning a substrate using dual tone development. Further, the invention relates to optimizing a dual tone development process.

Method of process optimization for dual tone development

A method and system for patterning a substrate using a dual-tone development process is described. The method and system comprise using a resist material having a polymer backbone with a plurality of protecting groups attached thereto to improve process latitude and critical dimension uniformity for the dual-tone development process.

Dual tone development processes

Variable resist protecting groups

A method and system for patterning a substrate using a dual tone development process is described. The method comprises use of plural photo-acid generators with or without a flood exposure of the substrate to improve process latitude for the dual tone development process.

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Austin, TX, United States of America

Carlos A Fonseca