Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Sgs Microelettronica Spa

Other

Boehringer Mannheim Italia, S.p.a.

Boehringer Mannheim Italia

Co.ri.m.me-consorzio Per La Ricera Sulla Microelectronia Nel.

Beehringer Biochemia Robin S.p.a.

Carlo Riva

Federico Pio

Lorenzo Fratin

Paolo Ghezzi

Alfonso Maurelli

Paolo Giuseppe Cappelletti

Marco Frigerio

Carmelo A Gandolfi

Cesare Clementi

Giuseppe Corda

Gabriella Ghidini

Leonardo Ravazzi

Andrea Zaliani

Marco Olivo

Sergio Tognella

Odoardo Tofanetti

Silvia Lucherini

Anna Carrara

Camilla Calegari

Luigi Pascucci

Corrado Villa

Raffaele Zambrano

Bruno Vajana

Piero Capocelli

Giorgio Long

Paolo Rosini

Franco Maggioni

Grazia Valentini

Roberto D Domenico

A flash EEPROM having an array of memory cells which include a common source line connecting together source electrodes of the memory cells. A resistive feedback element is coupled in series between the common source line and a positive potential when the memory cells must be electrically erased. The Flash EEPROM includes a voltage limiting circuit coupled to the common source line for limiting the potential of the common source line to be prescribed maximum value lower than the positive potential.

Flash EEPROM with integrated device for limiting the erase source voltage

A flash EEPROM memory cell comprises source and drain regions defining a channel region therebetween, a floating gate and a control gate. The source and drain regions are first and second doped semiconductor regions of a first conductivity type formed in a first active area region of a semiconductor material layer of a second conductivity type; the control gate comprises a third doped semiconductor region of the first conductivity type formed in a second active area region of the semiconductor material layer; and the floating gate comprises a polysilicon strip insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region.

Manufacturing process for making single polysilicon level flash EEPROM cell

An HV transistor integrated in a semiconductor substrate with a first type of conductivity, comprising a gate region included between corresponding drain and source regions, and being of the type wherein at least said drain region is lightly doped with a second type of conductivity. The drain region comprises a contact region with the second type of conductivity but being more heavily doped, from which a contact pad extends.

HV transistor structure and corresponding manufacturing method

The cell is formed of a selection transistor, a detection transistor and a tunnel condenser. The detection Transistor has its own control gate formed with an n diffusion which is closed and isolated from those of the other cells of the same memory.

EEPROM memory cell with a single level of polysilicon programmable and erasable bit by bit

A process for forming an integrated circuit includes at least one matrix of non-volatile memory cells having an intermediate dielectric multilayer including at least a lower dielectric material layer and an upper silicon oxide layer. The integrated circuit includes at least one transistor simultaneously formed in zones peripheral to the matrix and having a gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower dielectric material layer, the process includes removal of said layers from the peripheral zones of the matrix; deposition of said upper silicon oxide layer over the memory cells, and over the substrate in the areas of the peripheral transistors; and formation of a first silicon oxide layer at least in the areas of the peripheral transistors. A second transistor type can be formed having a gate dielectric of a second thickness, thinner than said first thickness, in successive steps.

Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC

A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material. The electronic circuit is of the type that calls for formation above the major surface of at least one dielectric multilayer. The dielectric multilayer includes a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a more internal first area and a more external second area in the morphological structure. The device edge morphological structure includes in the substrate an excavation on the side of the major surface at the more internal first area of the morphological structure in a zone in which is present the continuous portion of the dielectric multilayer.

Process for forming an edge structure to seal integrated electronic devices, and corresponding device

Process for forming an edge structure to seal integrated electronic

Process for forming an integrated circuit comprising non-volatile memory

A MOS transistor capable of withstanding relatively high voltages is of a type integrated on a region included in a substrate of semiconductor material, having conductivity of a first type and comprising a channel region intermediate between a first active region of source and a second active region of drain. Both these source and drain regions have conductivity of a second type and extend from a first surface of the substrate. The transistor also has a gate which includes at least a first polysilicon layer overlying the first surface of at least the channel region, to which it is coupled capacitively through a gate oxide layer. According to the invention, the first polysilicon layer includes a mid-portion which only overlies the channel region and has a first total conductivity of the first type, and a peripheral portion with a second total conductivity differentiated from the first total conductivity. The peripheral portion partly overlies the source and drain active regions toward the channel region.

High-voltage-resistant MOS transistor, and corresponding manufacturing

Inductive structures make highly efficient use of the magnetic flux generd, and are consistent with integrated circuit manufacturing techniques. The structures include electrically conductive layers and interconnecting conductor filled vias to define a helical winding surrounding a closed magnetic core. The magnetic core may also be formed by semiconductor manufacturing techinuqes. A method of making the structures on a semiconductor substrate concurrently with the formation of the integrated circuit itself is also disclosed.

Method for realizing magnetic circuits in an integrated circuit

Single polysilicon level flash EEPROM cell and manufacturing process

A nonvolatile memory having a cell comprising an N.sup.+ type source region and drain region embedded in a P.sup.- type substrate and surrounded by respective P-pockets. The drain and source P-pockets are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell also presents a higher breakdown voltage as compared with known cells.

Method of making asymmetric nonvolatile memory cell

The method includes the following steps: delimiting active areas on a substrate, forming gate electrodes insulated from the substrate on the active areas, and subjecting the front surface of the substrate to several implantation steps with doping ion beams to form source and drain regions with the use of the gate electrodes as masks. The direction of the implantation beam is defined by an angle of inclination to the front surface and by an orientation to a reference line on the front surface. To avoid performing numerous implantation steps without foregoing channels of uniform and constant length, the widths of the gate electrode strips are determined at the design stage in relation to the orientation of the strips to the reference line and on the orientation of the directions of the implant beams.

Method of producing MOSFET transistors by means of tilted implants

A process or forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor. The process further includes removal of the preceding layer from areas assigned only to the transistors of the second type; deposition of said upper silicon oxide layer over the memory cells, over the first silicon oxide layer in the areas of the transistors of the first type and over the substrate in the areas of the transistors of the second type; and formation of a second silicon oxide layer in the areas of both types of peripheral transistors.

A method for programming a two-level polysilicon EEPROM memory cell, which cell is implemented in MOS technology on a semiconductor substrate and comprises a floating gate transistor and a further control gate overlying the floating gate with a dielectric layer therebetween, provides for the application of a negative voltage to the control gate during the cell write phase. This enables the voltages being applied across the thin tunnel oxide layer to be distributed so as to reduce the maximum amount of energy of the 'holes' and improve the oxide reliability. In addition, by controlling the rise speed of the impulse to the drain region during the write phase, and of the impulse to the control gate during the erase phase, the maximum current flowing through the tunnel oxide can be set and the electric field being applied to the tunnel oxide kept constant, thereby the device life span can be extended.

Double polysilicon EEPROM cell and corresponding manufacturing process

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Renate, Italy

Carlo Riva