Stmicroelectronics S.r.l.

Ovonyx Memory Technology, LLC

Micron Technology Incorporated

Other

Carlo Lisi

Umberto Di Vincenzo

Emanuele Confalonieri

Lorenzo Bedarida

Marco Sforzin

Nicola Del Gatto

Alessandro Magnavacca

Marco Ferrario

Antonino Geraci

Andrea Bellini

Mauro Luigi Sali

Tecla Ghilardi

Vincenzo Dima

Carla Giuseppina Poidomani

Paolo Turbanti

Massimiliano Scotti

Luca Vandi

Francesco Pipitone

Antonio Geraci

Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.

Devices and methods to program a memory cell

A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels.

Method of managing a multilevel memory device and related device

A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to said gate terminal and a voltage value of said drain terminal is regulated so as to be maintained at a fixed value until a threshold voltage value of said memory cell is set at a desired threshold voltage level; and a disable phase that stops said programming and is triggered as soon as a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the attainment by the threshold voltage value of said memory cell of the desired threshold voltage value. A programming circuit is suitable for implementing this method.

Method and circuit for programming a memory cell, in particular of the NOR flash type

A method and circuit for programming a multilevel memory of a flash EEPROM type having a matrix of cells grouped in memory words. The method provides for the simultaneous generation of a first programming voltage value and a second verify voltage value to bias word lines of the memory matrix during programming and verify operations, respectively, of the memory itself. A circuit implementing the above method is also provided.

Programming method of multilevel memories and corresponding circuit

A method for verifying an array cell of a memory device may include determining after each erase pulse or program pulse the threshold of a cell addressed through a selected array word-line and bit-line, by applying an identical voltage ramp to the selected array word-line and to the control gate of a reference cell, while biasing at a certain voltage deselected word-lines through distribution lines of the voltage generated by a charge pump generator. The method may further include temporarily decoupling the deselected word-lines from the distribution lines of the bias voltage for the duration of the voltage ramp.

Control of voltages during erase and re-program operations of memory cells

A circuit for detecting a logic transition is proposed. The circuit includes an input terminal for receiving a logic signal, an output terminal for generating a detection signal, two capacitors, in a steady condition a first one of the capacitors and a second one of the capacitors being alternately at a first voltage and at a second voltage, respectively, and exchanging means for bringing the first capacitor to the second voltage and the second capacitor to the first voltage in response to a switching of the logic signal; the circuit further includes means for maintaining a command node at the first voltage in the steady condition, means for generating a reset pulse through the first capacitor in response to the switching, means for bringing the command node to the second voltage in response to the reset pulse, a generator of regulated current for bringing back the command node to the first voltage through the second capacitor, and logic means having a regulated threshold voltage comprised between the first and the second voltage, the logic means asserting the detection signal when the command node is brought to the second voltage and deasserting the detection signal when the command node reaches the threshold voltage.

Circuit for detecting a logic transition with improved stability of the length of a detection signal pulse

A device for timing random reading of a memory device with a data access time, in which reading is performed by a succession of consecutive operations, the timing device being designed to generate, for each operation, a corresponding timing signal such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration, which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration; the sum of the fixed durations being equal to the data access time of the memory device.

Method and device for timing random reading of a memory device

A nonvolatile memory device with simultaneous read/write has a memory array formed by a plurality of cells organized into memory banks, and a plurality of first and second sense amplifiers. The device further has a plurality of R/W selectors associated to respective sets of cells and connecting the cells of the respective sets of cells alternately to the first sense amplifiers and to the second sense amplifiers.

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Milan, Italy

Carlo Lisi