Lsi Logic Corporation

Fujitsu Corporation

Lsi Corporation

Carlo Grilletto

David A Horine

Zafer S Kutlu

David G Love

Jed Bayking

An interposer card used during qualification tests on integrated circuit packages is disclosed that eliminates the need for sockets and custom boards. The interposer card includes pads for mounting the I/Os of a test package; edge card connectors for connecting the interposer card directly to a test board and for performing bias testing on the test package; and pads for replicating the test package I/Os for connecting the interposer card to an automated electrical testing (ATE) system for performing ATE tests on the test package.

Socketless/boardless test interposer card

A zero automated electrical testing (ATE) interposer daughter card (IDC) is provided for use in a test apparatus for ATE. Embodiments of the IDC include a first side having a first set of pads for mounting I/O's of a test package; and a second side having a second set of pads coupled to the first set of pads for replicating the first set of pads, wherein the second set of pads is located in area of the interposer card horizontally offset from the first set of pads, such that ATE measurements are obtained by removably inserting only a portion of the interposer card containing the second set of pads into an ATE test socket.

Zero ATE insertion force interposer daughter card

A method and system for testing an integrated circuit package is disclosed. The integrated circuit package includes a plurality of daisy chain loops that are connected to a pair of package pads, wherein adjacent daisy chain loops are oppositely biased. Aspects of the present invention include forming a first plurality of gangs of electrically coupled daisy chain loops having a first bias and forming a second plurality of gangs of electrically coupled daisy chain loops having a second bias. Each one of the first plurality of gangs is individually coupled to an electrical measurement device, while the second plurality of gangs are electrically coupled in common, and the common gang is coupled to the electrical measurement device. According to the method and system disclosed herein, the electrical measurement device may be used to indicate whether there is any leakage between one or more of the first plurality of gangs and the common gang, thereby eliminating the need to use an ATE tester and device under test (DUT) circuit board to perform reliability tests.

Daisy chain gang testing

A test coupon for performing pre-qualification test on a substrate is disclosed. The test coupon includes at least two substrate test structures, and an edge connector for providing external electrical connections. Traces patterned on the test coupon connect the test structures with the edge connector, such that a test apparatus maybe coupled to the edge connector for testing the test coupon without the need to manually solder connections to the test coupon. The test coupon may also be used to perform the actual qualification of certain process changes in substrate construction and to monitor production lot quality and reliability.

Universal test coupon for performing prequalification tests on substrates

A system for maintaining electronic components, such as integrated circuit chips, in a contaminant-free controlled atmosphere is disclosed. The components, which may be mounted on a multichip module, are housed in a sealed enclosure and a positive pressure of contaminant-free gas, such as pure nitrogen, is maintained within the enclosure. A source of pressurized gas, controllably connected to the enclosure is provided and, preferably, an exhaust valve is used to equalize the pressure in the enclosure when it is necessary to access the interior for purposes of maintenance or repair. Preferably, there is a control system which monitors and maintains the proper level of pressure within the enclosure and which may be used to periodically flush the enclosure. Also preferably, one or more canisters of getter material are attached to the enclosure for removing contaminants.

System for maintaining a controlled atmosphere in an electronic circuit

A method and apparatus for filling small diameter, high aspect ratio via openings with a plating solution are disclosed. An apparatus according to the invention comprises a sealable chamber for receiving one or more a multichip module substrate comprising via openings to be plated. A vacuum pump is used to evacuate the chamber after the substrate(s) are positioned therein and the chamber has been sealed. Plating solution is then introduced into the chamber to immerse the substrate(s), and the solution is pressurized, forcing the liquid into the via openings. In one preferred embodiment, the chamber comprises two subchambers separated by a flexible wall. After the subchamber holding the substrate(s) has been evacuated and filled with plating solution, the other subchamber is pressurized, as with compressed air, such that a force is applied to the flexible wall creating hydrostatic pressure within the first subchamber.

Growing community of inventors

San Carlos, CA, United States of America

Carlo Grilletto