Cselt-centro Studi E Laboratori Telecomunicazioni S.p.a.

Carlo Demichelis

Paolo Mattone

Giuseppe Giandonato

Silvano Giorcelli

Alessandro Zappalorto

Valerio Barcaroli

Paolo Mancini

A label-switching and control interface for asynchronous fast-packet switching consisting of a set of label-switching and cell-processing units controlled by a suitable control unit. The units operate at each multiplex level in real time thanks to a microprogrammed logic requiring the control processor intervention only at the connection set-up/release. The units implement the low levels of the flow control algorithms necessary to conveniently exploit the advantages of the techniques. The label becomes indicative of a virtual circuit which is allotted only locally to the call, annulling thus the necessity of very extensive labels, while the parameters which characterize the connection which uses a particular label are stored in the unit itself. Each unit switches the label characterizing the connection on the node input multiplex, with that whereby it is characterized on the output multiplex and at the same time associates, with each cell, the information necessary to multiplex switching which is then carried out in a self-routing network. The cells processed in this way by each unit of the set are statistically multiplexed in an asynchronous way and sent to a connection network termination. Such a termination serves a plurality of asynchronous multiplexes, which can be at a different frequency from each other and more particularly it is worth noting that each label-switching unit does not have its own operating frequency, but automatically takes up that of the asynchronous multiplex to which it is connected.

Label-switching and control interface for asynchronous fast-packet

An interface interposed between a PCM data terminal and a processor comprises a bus accessor dialoguing with the processor, input and output circuitry coupled to the terminal, and intervening logic circuits and data stores designed to supply the processor in a time-division mode with preprocessed messages received or to be transmitted over a multiplicity of channels. The interface is operable according to dialogue procedures of HDLC type such as those corresponding to CCITT recommendations X25, X75 and N. 7, with switchover from one protocol to another.

Multichannel interface linking a PCM line with a processor

An apparatus for handling incoming signals from sensors monitoring the state of certain points of a telephone circuit as well as outgoing signals for drivers associated with other circuit points includes a preprocessor PE inserted between the assembly DR of sensors and drivers, on the one hand, and a processor EL, on the other hand. The preprocessor and the processor have access, through a bus 5, to a common memory ME having areas allocated to the scanning of the circuit points, to time-counting operations and to the storage of messages from the preprocessor. A microprogram memory in the preprocessor, when addressed by a sequencer CM started automatically, manually or in response to an instruction from the processor, initiates a temporary seizure of the bus--if the latter is available--whereupon an initial address is delivered from the common memory ME to a working memory ML in the preprocessor to start the scanning of successive pairs of circuit points. If the pair being scanned is connected to sensors, a change of state in either point is reported to the processor if verified by an integration procedure under the control of a read-only memory MIN in the preprocessor; if the points are connected to drivers, the same read-only memory MIN controls the emission of outgoing signals to them. Upon the completion of the scanning operation, the preprocessor performs lower-priority tasks of generating clock messages and measuring signal durations before relinquishing control of the bus.

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Turin, Italy

Carlo Demichelis