Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

St-ericsson Sa

Sgs-thomson Microelectronics S.p.a.

Oct Circuit Technologies International Limited

Carlo Crippa

Rossella Bassoli

Pierangelo Confalonieri

Germano Nicollini

Daniel Senderowicz

Carlo Dallavalle

A programmable data processing circuit is configured for receiving sensor signals indicative of gestures for identification by the processing circuit. The processing circuit applies to the sensor signals finite state machine processing resources to provide identification output signals indicative of gestures identified as a function of the sensor signals. A plurality of finite state machine processing programs loaded into the processing circuit include a data section and an instruction section. The data section including a fixed size part specifying respective processing resources used by the programs in the plurality of finite state machine processing programs and a variable size part with respective sizes for allocating the respective processing resources used by the programs in the plurality of finite state machine processing programs. The instruction section including conditions and commands for execution by the respective processing resources used by the programs by operating on data located in the respective data sections.

Gesture recognition method, corresponding circuit, device and computer program product

A magnetic field sensor generates signal components corresponding to an uncalibrated representation of a sensed magnetic field in a three-dimensional coordinate system. A reader coupled to the magnetic field sensor determines a center offset based on received signal components, adjusts the received signal components based on the determined center offset, and applies Kalman filtering to the adjusted signal components, generating a set of ellipsoid parameters. The reader generates calibrated signal components based on the determined center offset and the generated set of ellipsoid parameters.

Calibration method for magnetic field sensing devices, corresponding system, apparatus and computer program product

A digital class D amplifier () is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input () for receiving the filtered digital signal (w[n]) and having a first output () connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output () the feedback signal (fb[n]). The PWM conversion module (PW_CM) comprises: a first comparator (CMP_N) adapted to compare the filtered digital signal (w[n]) with a first reference triangular waveform (VTn[n]) for providing as output a first PWM signal (yn[n]), the first reference triangular waveform having a frequency (f_osc) much lower than said clock frequency (f.s); a second comparator (CMP_P) adapted to compare the filtered digital signal (w[n]) with a second reference triangular waveform (VTp[n]) for providing as output a second PWM signal (yp[n]), the second reference triangular waveform (VTp[n]) being the inverse of the first triangular waveform (VTn[n]), said first (yn[n]) and second (yp[n]) PWM signals representing a differential output pulse width modulated signal (yn[n],yp[n]).

Digital class-D amplifier and digital signal processing method

The present disclosure generally relates to the field of digital Class-D amplifiers and more specifically to a technique for reducing output waveforms distortion of a digital class-D amplifier implementing a ternary modulation scheme. An apparatus embodiment comprises an enlarging component for enlarging at least one pulse of a first output waveform PWM_P_TERN' of the amplifierby a first enlarging pulse, wherein the at least one pulse of the first output waveform PWM_P_TERN&#x2032; is symmetrically enlarged by the first enlarging pulse with respect to the center position of the at least one pulse; and a pulses generating component for generating at least one first compensating pulse comp_pulse_p and for adding the generated at least one first compensating pulse comp_pulse_p on a second output waveform PWM_N_TERN&#x2032; of the amplifier, wherein the at least one first compensating pulse comp_pulse_p has substantially the same width P as the first enlarging pulse and is added on the second output waveform PWM_N_TERN&#x2032; at a position which corresponds to the center position of the at least one pulse of the first output waveform PWM_P_TERN&#x2032;.

Method and apparatus for efficient and distortion compensated digital class-D amplifier ternary modulation scheme

A digital circuit for controlling the gain of an amplifier stage of a coded signal receiving channel is provided. The circuit includes a peak detector coupled to the input terminal of the receiving channel through a coded signal rectifying circuit and a gain control stage. The gain control stage includes a digital comparator having two input terminals respectively connected to an output terminal of the peak detector and to a memory, and an output terminal coupled to a gain control terminal of the amplifier stage. The address selectable contents of the memory contain predetermined peak values in coded form.

Digital circuit to regulate the gain of an amplifier stage

A voltage multiplier for relatively high output current has its design output voltage stabilized and rendered independent of process spread, temperature, supply voltage and output current level, by a stabilization loop driving the switch that cyclically connects to ground a charge transfer capacitance of the functional voltage multiplier circuit. The feedback loop comprises an integrating stage, stabilized by creating a low-frequency zero in the transfer function for compensating one of two low-frequency poles of the transfer function of the whole circuit.

Voltage multiplier for high output current with stabilized output voltage

The circuit includes a filter to which an analog signal is applied, a quantizer driven by the filter, a sampler at a desired frequency driven by the quantizer and a PCM encoder driven by the sampler. The quantizer generates a quantize signal according to the received analog signal and further generates a difference signal according to the difference between a quantized signal and the analog signal. A feedback circuit feeds back the difference signal from the quantizer to a stage of the filter so that the overall transfer function from the input of the feedback circuit to the output of the filter is equivalent to a low pass filtering.

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Merate, Italy

Carlo Crippa