Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Sgs-thomson Microelectronics Limited

Carlo Cremonesi

Bruno Vajana

Giovanna Dalla Libera

Roberta Bottini

Nicola Zatelli

Federico Pio

Giulio Albini

Giorgio Servalli

Matteo Patelmo

Cesare Clementi

Alessandro Grossi

Nadia Galbiati

A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.

Process for forming differential spaces in electronics device integrated on a semiconductor substrate

A method manufactures non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry. The manufacturing method includes: forming a plurality of electrodes of the matrix memory cells, each electrode including a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer; and forming a plurality of electrodes of transistors of the circuitry each including a first dielectric layer and a first conductive layer. The method also includes forming first coating spacers on the side walls of the gate electrodes of the memory cell and second coating spacers on the side walls of the gate electrodes of the circuitry, the second spacers being wider than the first spacers.

Method for manufacturing non-volatile memory devices integrated in a semiconductor substrate

A process for manufacturing a programmable non-volatile memory device having floating-gate MOS transistors, and first and second MOSFETs, the second MOSFETs capable of sustaining gate voltages higher than the first MOSFETs, by forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the first MOSFETs, and a third gate oxide layer for the second MOSFETs. The process includes: forming a first oxide layer over a substrate; selectively removing the first oxide layer from surface regions over the first MOSFETs, but not from surface regions over the floating-gate MOS transistors or the second MOSFETs; forming a second oxide layer over the first oxide layer and the regions over the first MOSFETs; removing the first and second oxide layer from a tunnel oxide region of the floating-gate MOS transistors; and forming a tunnel oxide layer over the second oxide layer and tunnel region oxide layer.

Process for the manufacturing of an electrically programmable non-volatile memory device

A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.

Memory cell for EEPROM devices, and corresponding fabricating process

A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell. After forming and before partially defining the first polysilicon layer, the process implants at least at the channel region of the floating-gate storage transistor for adjusting the transistor threshold.

Memory cell of the EEPROM type having its threshold adjusted by implantation, and fabrication method

A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.

Memory cell for EEPROM devices and corresponding fabricating process

The structure allows checking an integrated electronic device comprising an oxide layer to be measured located above a doped pocket of a wafer of doped semiconductor material and arranged adjacent to a gate region of polycrystalline semiconductor material. The structure is formed at a suitable point of the wafer and comprises an oxide test region of the same material, having the same thickness and the same electrical characteristics as the oxide layer to be measured and a polycrystalline region of the same material, having the same thickness and the same electrical characteristics as the gate region. The polycrystalline region extends preferably along the perimeter of a square and delimits laterally the oxide test region, the area of which is greater than the area of the oxide layer to be measured so as to allow non-destructive testing, on-line, of the oxide layer to be measured during an early stage of the manufacturing process.

Structure and method for evaluating an integrated electronic device

A method of forming source and drain regions for LV transistors that includes the steps of forming sacrificial spacers laterally to LV gate regions; forming LV source and drain regions in a self-aligned manner with the sacrificial spacers; removing the sacrificial spacers; forming HV gate regions of HV transistors; forming gate regions of selection transistors; forming control gate regions of memory transistors; simultaneously forming LDD regions self-aligned with the LV gate regions, HV source and drain regions self-aligned with the HV gate regions, source and drain regions self-aligned with the selection gate region and floating gate region; depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask; anisotropically etching the dielectric layer, to form permanent spacers laterally to the LV gate regions; removing the protection silicide mask; and forming silicide regions on the LV source and drain regions and on the LV gate regions.

Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks

A process forms a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of, in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer; depositing and partly defining a first polysilicon layer; forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor; depositing a second polysilicon layer; selectively etching away, through a first mask, at least the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor; and selectively etching away, through a second mask, the interpoly dielectric layer and the first polysilicon layer at the cell. After the selective etch through said second mask, an implantation step is only carried out through the second mask and at least at the channel region of the floating-gate storage transistor to set the transistor threshold.

Memory cell of the EEPROM type having its threshold set by implantation, and fabrication method

The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned etching mask defining the control gate regions and the floating gate regions of memory elements, keeping the circuitry area covered by a circuitry mask.

Process for manufacturing selection transistors for nonvolatile serial-flash, EPROM, EEPROM and flash-EEPROM memories in standard or AMG configuration

Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on said integrated structure, an eighth stage of selective etching and removal of said second polysilicon layer in a region for said memory cell, and of said first and second polysilicon layers in said region for said circuitry transistor in order to form said circuitry transistor, and a ninth stage of selective etching and removal of said intermediate dielectric layer and of said first polysilicon layer in said region for said memory cell, wherein during said fifth stage said intermediate dielectric layer is etched and removed also in a region that is destined to form a channel of said selection transistor, and said sixth stage of ionic implantation therefore allows to introduce said dopant into said channel region and therefore to increase the threshold voltage of said selection transistor.

EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process

Process for manufacturing an electrically programmable non-volatile memory device having electrically programmable non-volatile memory cells comprising floating-gate MOS transistors, a first kind of MOSFETs, and a second kind of MOSFETs capable of substaining gate voltages higher than that sustainable by the MOSFETs of the first kind. The process includes forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the MOSFETs of the first kind, and a third gate oxide layer for the MOSFETs of the second kind. The first gate oxide layer further comprises a tunnel oxide region. The process provides for: forming over the surface of a semiconductor material a first layer of oxide; selectively removing the first layer of oxide from regions of said surface dedicated to the MOSFETs of the first kind, but not from the regions dedicated to the floating-gate MOS transistors nor to the MOSFETs of the second kind; forming a second layer of oxide over the first layer of oxide and over said regions dedicated to the MOSFETs of the first kind; simultaneously removing the first and the second layer of oxide only from the tunnel oxide region of the floating-gate MOS transistors; and forming over the second layer of oxide and over said tunnel region oxide for the floating-gate MOS transistors a tunnel oxide layer. The third gate oxide layer and said first gate oxide layer, except in the tunnel oxide region, are formed by the superposition of the first layer of oxide, while the second layer of oxide and the tunnel oxide layer, said second gate oxide layer being formed by the superposition of the second layer of oxide and the tunnel oxide layer.

Process for manufacturing a non-volatile memory with memory cells arranged in rows and columns in a matrix structure, with source lines extending in parallel with and intercalated to said rows, the cells including MOS transistors having a floating gate and a control gate respectively formed in a first and a second polysilicon layers superimposed, the process including a first step of definition of regions of active area covered by a layer of thin oxide and delimited by regions of field oxide, a second step of deposition of the first polysilicon layer, a third step of etch of the first polysilicon layer through a first mask to separate the floating gates of cells belonging to a same row of the matrix, a fourth step of deposition of an intermediate dielectric layer and of the second polysilicon layer, a fifth step of definition of the rows through self-aligned selective etch of said second polysilicon layer, of the intermediate dielectric layer and of the first polysilicon layer, the self-aligned selective etch determining in the source lines excavations in correspondence of regions in which the first polysilicon layer has been removed during the third step, and a sixth step of dopant introduction in the regions of active area for the formation of regions of source and drain of the cells. Before the fourth step a selective introduction of dopant is provided in correspondence of regions of the common source lines in which the excavations will be formed, for the formation of doped regions deeper than the excavations.

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Vaprio d'Adda, Italy

Carlo Cremonesi