International Business Machines Corporation

Carlo A Pignedoli

Alessandro Curioni

Wanda Andreoni

Vijay Narayanan

Eduard Albert Cartier

Sufi Zafar

Rajarao Jammy

Paul Charles Jamison

Fenton Read McFeely

Alessandro Cesare Callegari

Christopher Peter D'Emic

Michael Abramovich Gribelyuk

Dianne L Lacey

Evgeni Petrovich Gousev

Joseph Francis Shepard, Jr

Evengi Gousev

Joseph P Shepard, Jr

A method of forming a high-K gate stack for a MOSFET device to control the threshold voltage for the MOSFET device. A first high-K metallic oxide layer is formed on a semiconductor substrate. At least one composite layer is then formed directly on the first layer. The composite layer is composed of a second high-K metallic oxide layer formed directly on a dipole induction layer. The dipole induction layer includes a high-K metallic oxide having higher oxygen vacancy affinity and lower oxygen vacancy diffusivity than the first and second layers. A metallic gate electrode is then formed on the composite layer. Formation of the various layers is such as to position the dipole induction layer of the composite layer between the gate electrode and substrate so as to shift the threshold voltage to a desired level. A high-K gate stack in a MOSFET device formed by the above method is also provided.

Formation of high-K gate stacks in semiconductor devices

The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800&#xb0; C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8&#xd7;10charges/cmor less, a peak mobility of about 250 cmV-s or greater and substantially no mobility degradation at about 6.0&#xd7;10inversion charges/cmor greater.

Method of forming metal/high-&#x3ba; gate stacks with high mobility

The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800&#xb0; C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8&#xd7;10charges/cmor less, a peak mobility of about 250 cm/V-s or greater and substantially no mobility degradation at about 6.0&#xd7;10inversion charges/cmor greater.

Method of forming metal/high-k gate stacks with high mobility

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Adliswil, Switzerland

Carlo A Pignedoli