Advanced Micro Devices Corporation

Legerity, Inc.

Carlin D Cabler

Alfredo R Linz

Glen W Brown

Martin P Soques

Larry David Hewitt

Geoffrey E Brehmer

Dale E Gulick

Michael A Nix

Paul G Schnizlein

David N Suggs

David E Norris

Michael E Spak

Jeffrey M Blumenthal

Ryan E Feemster

Michael Hogan

David J Guercio

Alan T Torok

Stephen Victor Kosonocky

Moises Emanuel Robinson

Alan F Hendrickson

Sebastien Nussbaum

Walter Stuart Schopfer

Anil Kumar

Rajiv M Hattangadi

Herbert M Chen

Jeffrey Jay Anderson

Thomas Hirsch

Leonard Disanza

Geoffrey G Brehmer

A high voltage protection circuit for a non-tolerant integrated circuit is described herein. A non-tolerant integrated circuit may be a powered down integrated circuit or a low voltage tolerant integrated circuit, that may be exposed to a high voltage source such as an external circuit, device or power supply. The high voltage protection circuit includes a limiting transistor circuit, a control transistor circuit, and an isolation transistor circuit. The limiting transistor circuit limits or holds the voltage at the signal bump to be less than a voltage that can damage the circuit. The isolation transistor circuit disconnects input/output signal circuitry from normal protection circuitry. Both the limiting transistor circuit and the isolation transistor circuit are controlled by the control transistor circuit and are responsive to the power supply voltage being off.

High voltage protection circuit for non-tolerant integrated circuit

A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.

Method and apparatus for monitoring performance for secure chip operation

A method and apparatus is provided for impedance matching for a system capable of supporting voice and data bands. The method includes receiving an input signal having a voice and data band, filtering at least a portion of the data band of the input signal to provide a filtered signal, and adjusting the impedance of the system for the voice band in response to the filtered signal to provide an output signal.

Method and apparatus for impedance matching

A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Monolithic PC audio circuit

An active current steering semi-digital FIR filter for a digital-to-analog conversion circuit, which includes a shift register having a 1-bit digital input stream and a plurality of output taps, where each output tap provides a 1-bit signal which has a value of a logic 1 or a logic 0, and a plurality of current paths, where each path includes an active element, such as a transistor, having a relatively high output impedance, which is connected to a common current source, and to an op amp for current-to-voltage conversion. The relatively high output impedance of the active current steering element causes any error term resulting from offset at the op amp inputs to be minimized.

Apparatus and method for a combination D/A converter and FIR filter

A personal computer audio system is presented with a mechanism for digitally regulating the rate of voltage change of an audio output signal In one embodiment, the audio output signal from an integrated circuit is provided by means of a two-state audio amplifier. The first state of the amplifier is a high impedance state which exists prior to power-on and is maintained until an enable signal is asserted. When the enable signal is asserted, the amplifier drives the audio output signal line. Prior to the transition from the first to second states, a D/A converter is used to provide a ramp signal from the minimum voltage to the nominal operating voltage. The state transition is then initiated during the initial portion of the ramp signal.

Digital method to eliminate power-on pops and clicks

A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

Monolithic PC audio circuit with enhanced digital wavetable audio

Described herein is a fourth-order sigma-delta modulator which utilizes two second-order sigma-delta modulators connected together. Each second-order sigma-delta modulator is characterized as including integrators having a 1/2 sample period delay from input to output. A second-order sigma-delta modulator, including such integrators, exhibits a single sample period delay from input to output. A fourth-order sigma-delta modulator, which includes two such second-order sigma-delta modulators, exhibits a delay of two sample periods from input to output. The present sigma-delta modulator can be fabricated using switched capacitor circuitry to form an A/D convertor, and in another embodiment can be used as a digital noise shaper for a D/C convertor circuit. The 1/2 unit delay is implemented without requiring two D-flip flops in series, which results in a design and manufacturing advantage.

Sigma-delta modulator having reduced delay from input to output

A stereo audio CODEC, including means for performing D/A and A/D conversions, means for reducing digitally induced noise during attenuation/gain changes, data format conversion means, analog and digital filtering means, analog mixing means, on-chip 16-sample, 32-bit wide record and playback FIFOs, serial interface with external serial DSP, large local memory for supplementing on-chip record and playback FIFOs, control registers, register data bus and synthesizer DAC.

Stereo audio CODEC

An analog-to-digital conversion circuit is described which includes a front end sigma-delta modulator circuit, a multi-stage digital decimation filter circuit, and a digital compensation filter circuit. An overrange detect circuit is also provided.

Delta-sigma ADC with multi-stage decimation filter and gain compensation

A current steering semi-digital reconstruction filter for a digital-to-analog conversion circuit, which includes a shift register having a 1-bit digital input stream and a plurality of output taps, where each output tap provides a 1-bit signal which has a value of a logic 1 or a logic 0, and a plurality of resistive paths, where each resistive path includes a resistive element which is connected to a common current source and to a first terminal of an active high switch and a first terminal of an active low switch. A single output tap is used to control the active high switch and the active low switch for a single resistive path. A second terminal of each active high switch of each of the plurality of resistive paths is connected to a non-inverted current path, and a second terminal of each active low switch for each of the plurality of resistive paths is connected to an inverted current path.

Current steering semi-digital reconstruction filter

Stereo audio codec

This invention is for a digital-to-analog conversion circuit (DAC) which includes an interpolation filter circuit, a noise shaper circuit and a semi-digital FIR filter circuit. The entire DAC circuit provides noise shaping, analog filtering and oversampling functions.

Multi-stage digital to analog conversion circuit and method

This invention includes a linear, low noise, low voltage operational amplifier which drives variable resistive and capacitive output loads and includes a slave emitter follower buffer stage.

Low voltage linear output buffer operational amplifier

A method of cascading sigma-delta modulators includes the step of feeding the input to the quantizer of each modulator stage to the subsequent stage. Therefore, the signal which is fed to each of the subsequent stages is the difference between the output and the quantization noise of the previous stage. The method also includes the step of removing the quantization noise of the first two stages, as well as the output of the first two stages, so that the final output of the cascaded modulators is a delayed version of the input, plus a scaled version of the last stage which has been shaped with a fourth-order high pass function.

Growing community of inventors

Austin, TX, United States of America

Carlin D Cabler