Intel Corporation

Carleton L Molnar

Gerald S Pasdast

Nevine Nassif

Krishnakanth Venkata Sistla

Ankush Varma

Yen-Cheng Liu

Dheeraj R Subbareddy

George Zacharias Chrysos

Vedaraman Geetha

Mahesh K Kumashikar

Jeffrey D Chamberlain

William R Halleck

Tejpal Singh

Srikanth Nimmagadda

Siva Soumya Eachempati

John R Ayers

Johanna M Swan

Adel A Elsherbini

Shawna M Liff

Dmitri E Nikonov

Tanay Karnik

Julien Sebot

Neelam Chandwani

Robert J Munoz

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

Fine-grained disaggregated server architecture

Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Multiple dies hardware processors and methods

Growing community of inventors

Northborough, MA, United States of America

Carleton L Molnar