Sgs-thomson Microelectronics S.r.l.

Sgs-thomson Microelectronics S.a.

Carla Maris Golla

Silvia Padoan

Marco Olivo

Luigi Pascucci

Giovanni Campardo

Mauro Luigi Sali

Maurizio Branchetti

Alessandro Cremonesi

Marco MacCarrone

Stefano Zanardi

Armando Conci

Luigi M Sali

Sali M Luigi

William Vespi

A circuit for generating a stable reference voltage (Vref) as temperature and process parameters vary, including at least one field-effect transistor (M ) and an associated resistive bias element (R) connected in series between a supply voltage (Vcc) and ground (GND), further includes a second field-effect transistor (M ) connected to the first transistor such that the reference voltage (Vref) can be picked up as the difference between the respective threshold voltages of the two transistors. This provides a reference voltage which is uniquely stable against variations in temperature and process parameters.

Stable reference voltage generator circuit

An output stage for electronic circuits with high voltage tolerance and of the type comprising an output buffer made up of a complementary transistor pair comprising a P-channel MOS pull-up transistor and an N-channel MOS pull-down transistor. The transistors are connected together to make up an output terminal of the stage which comprises in addition a switch having an input connected to the output terminal of the stage and an output connected to the control terminal of the pull-up transistor to drive said control terminal in a state of extinction of the output buffer.

High voltage tolerance output stage

The invention relates to a method of recovering faulty non-volatile memories. This method can be applied to an electrically programmable semiconductor non-volatile memory device set up as a multi-sector memory matrix and including selection circuitry for selecting words or individual bytes of the memory. According to this method, the memory matrix is addressed by byte, rather than by memory word, by selection circuitry, whenever the device fails an operation test. The use of a Hamming code for error correction to remedy malfunctions due to manufacture allows the method to be applied to those devices which fail their test and would otherwise be treated as rejects.

Method for recovering failed memory devices

A charge pump voltage booster circuit with control feedback of the type comprising an output line connected to a load and on which is produced an output voltage boosted in relation to a supply voltage and a feedback loop incorporating a charge pump connected to said line and a control logic circuit of said pump interlocked with a comparator having an input connected to the line comprises also an auxiliary charge pump connected in turn to said line and designed to supply a quantity of current greater than or equal to the leakage currents of the load in stand-by condition. The auxiliary pump has current consumption much lower than that of the main charge pump. In addition, upon emerging from the off state there is provided starting of the main charge pump for a brief time period sufficient to take the booster output to a sufficient value.

Charge pump voltage multiplier circuit

A memory device including first and second memory cell arrays in which are stored respectively user data and error identification and correction data. The memory device also includes first and second decoding means operationally connected to the first and the second memory cell arrays for producing select user data signals and select error identification and correction data signals. The memory device further includes error identification means operationally coupled to the first and the second decoding means. The memory device also comprises error correction means operationally connected to the first and the second decoding means and to the error identification means. Finally the memory device includes a control unit operationally connected to the second decoding means, to the error identification means and to the error correction means to enable the second decoding means and the error correction means if the error identification means detect an error in the select user data signals.

Memory device with improved yield and reliability

A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.

Device for detecting a reduction in a supply voltage

A method of filtering digital signals having a high dynamic range includes splitting the sampled input signal into at least two portions addressing each of the portions to a respective program filter, and performing each filtering operation in parallel and independently, and reconstituting an output signal by summing together the digital outputs from each filter.

Method and apparatus for filtering digital signals

A circuit for selectively programming a single bit in non-volatile memory is disclosed. The circuit consists of at least one comparator, at least one transistor, and at least one logic gate for each elementary memory in the memory word. In operation, the circuit allows for individual correction of mis-programmed cells within the memory by comparing the actual contents of the memory with the desired contents. If the actual contents does not match the desired contents, that individual cell is re-programmed.

Circuit for identifying a memory cell having erroneous data stored

A circuit generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit includes a variable, asymmetrical propagation line composed of a succession of elementary delay elements enabled or disabled on the basis of memorized logic signals, the state of which is determined when debugging the memory in which the circuit is implemented.

Internal timing method and circuit for programmable memories

A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.

Regulation circuit and method for the erasing phase of non-volatile

The input signal is filtered using at least two filtering operations (i.e. at least two types of transfer functions), and then is reconstituted by summing the two different digital outputs generated by each filtering arrangement, for example by using a summing circuit. In a preferred embodiment of the invention, a single programmable filter processor is used and is operated in two alternately selected modes, each sharing common filter coefficients. A clock signal alternately selects the two filtering modes. The subsequent outputs from a first mode are delayed and then added to the output of the second mode to produce the desired output signal.

Method and apparatus for filtering high resolution digital signals

A high-resolution digital filter including a memory structure receiving as input a sampled digital signal, and an adder chain with delay blocks connected between the adder chain and the memory structure. The adders are connected to memory outputs to convert the input signal into an output signal having predetermined frequency response characteristics. The memory structure includes at least one pair of non-volatile memory elements, each memory element being input one portion only of the sampled signal.

High-resolution digital filter

A fast adder chain for adding together at least one pair of digital words and including a plurality of cascaded adder blocks. Each block having computation adders for obtaining the pseudosum of said pair of digital words and latches for storing and transmitting the pseudosum to the next block and the pseudocarry from the computation to the chain end.

Fast adder chain

A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage being powered between a first and a second voltage reference and having a first input terminal connected to a resistive divider of the first reference voltage and an output terminal fed back to said input through a current mirror, and a source-follower transistor controlled by the output and connected to the cells through a programming line. Also provided is a MOS transistor which connects to ground the programming line and a corresponding resistive path connected between the current mirror and the second voltage reference.

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Sesto San Giovanni, Italy

Carla Maris Golla