Intel Corporation

Carl Seger

Ziyad Hanna

Alexander Levin

John Moondanos

Daher Kaiss

The present invention provides a formal equivalence verification method and system to determine the compatibility, or nonsimilarity, of two or more circuit designs. The method and system can check the corresponding verification nodes or candidates for cut points while accounting for input vectors including environmental conditions. The method and system may produce an answer for the user to indicate, for example, compatibility or disimilarity.

Method and device for verification of VLSI designs

The present invention provides a method and system for comparing a pair of circuit models without the need for performing a false negative check when cut-points are introduced. An exemplary method includes generating a BDD for each of a plurality of signals of each circuit model from an initial cut-point frontier towards an output of each circuit model until a BDD of one of the plurality of signals reaches a predetermined maximum size, selecting a new cut-point signal frontier, and generating a normalized function for each cut-point signal on the new cut-point frontier of each circuit model.

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Hillsboro, OR, United States of America

Carl Seger