Telefonaktiebolaget Lm Ericsson (Publ)

Carl P Lundh

Erik O Abefelt

Karl A Bjenne

Lars G Schyman

Eric O Abefelt

A method for distincting between at least two types of time slots in serial digital bit streams that are transmitted over a link between a transmitter and a receiver and that derive from the streams of parallel data bits which are delivered to the transmitter via an interface and subjected to parallel-series conversion in the transmitter. Subsequent to analyzing the parallel data bits in a time slot, the type of category to which this time slot belongs is decided and a plurality of marker bits are then inserted into the serial time slots, so as to obtain good transmission properties and also be restore the time slots to a parallel form. More specifically, the time slot categories are mutually separated with the aid of a different number of marker bits in the time slot, all of these marker bits having been assigned the inverted value of a bit other than the marker bits.

Method of distinguishing in serial digital bit streams between at least

The invention relates to a multiplexer for a digital switch, arranged to be included in a switch network whose data flow is organized in frames containing a number of time slots, said time slots including data time slots, which shall be directed through the switch from first to second sets of terminal units, such as subscriber connections, trunk connections, processors, etc. The multiplexer is controlled by a processor for controllable multiplexing, i.e., mapping of a number of transmission links from each of a corresponding number of the terminal units of said first set to a transmission link leading to the switch, as well as of a transmission link leading from the switch to a number of transmission links leading to each of a corresponding number of terminal units of said second set. The mapping is performed on the data time slots. All data time slots arriving from the terminal units of said first set are to be sent forward via a first buffer to the switch in an order which is determined by a first control memory for the mapping, and all data time slots arriving from the switch are to be sent forward via a second buffer toward the terminal units of said second set in an order which is determined by a second control memory for the mapping. The buffers are implemented as fifos, one for each of the links from and to the terminal units.

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Farsta, Sweden

Carl P Lundh