Advanced Micro Devices Corporation

Globalfoundries Inc.

Carl P Babcock

Luigi Capodieci

Hung-Eil Kim

Cyrus E Tabery

Todd P Lukanc

Christopher A Spence

Chris Haidinyak

Jayendra D Bhakta

Jongwook Kye

Bhanwar Singh

Christopher F Lyons

Kouros Ghandehari

A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques

A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.

System and method for designing an integrated circuit device

A method of adjusting a reticle layout to correct for flare can include determining a localized reticle pattern density across the reticle layout and determining a relationship between reticle pattern density and edge adjustment for the photolithography apparatus being used. For a given feature of the reticle layout, an edge of the feature can be adjusted by a given amount based on the localized reticle pattern density adjacent the given feature. This method allows for a rule-based optical proximity correction (OPC) approach to compensate for long-range and short-range flare within a photolithography apparatus.

Optical proximity correction (OPC) technique to compensate for flare

A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin

A method of automatically creating and/or optimizing an optical proximity correction (OPC) rule set can include providing an initial OPC rule set and applying the initial OPC rule set to a layout data set to generate a corrected layout data set. The corrected data set can be simulated and optical rule checking (ORC) can be performed. Based on the simulation and ORC, it can be determined whether residual edge placement errors are present within the corrected layout data set and whether the residual errors lie outside specified limits. If residual edge placement errors are present within the corrected layout data set or lie outside of specified limits, existing OPC rules can be modified and/or new OPC rules can be added to the initial OPC rule set to correct the residual edge placement errors.

System and method for automatic generation of optical proximity correction (OPC) rule sets

A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results

A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.

System and method for design rule creation and selection

A method of making a device using a lithographic system having a lens from which an exposure pattern is emitted. A conforming immersion medium can be positioned between a photo resist layer and the lens. The photo resist layer, which can be disposed over a wafer, and the lens can be brought into intimate contact with the conforming immersion medium. The photo resist can then be exposed with the exposure pattern so that the exposure pattern traverses the conforming immersion medium.

Immersion lithographic process using a conforming immersion medium

A method for developing an optimized layout fragmentation script for an optical proximity correction (OPC) simulation tool. A test pattern layout having at least one structure representing a portion of the integrated circuit layout is provided. Optical proximity correction is iteratively conducted on the test pattern layout for each desired permutation of at least one fragmentation parameter associated with the test pattern layout and, for each permutation, a corrected test pattern layout is generated. A printed simulation of each corrected test pattern layout is made and analyzed to select one of the permutations of the at least one fragmentation parameter to apply to a integrated circuit layout prior to correction with the OPC simulation tool.

Method of developing optimized optical proximity correction (OPC) fragmentation script for photolithographic processing

A film stack for forming shallow trench isolation among transistors and other devices on a semiconductor substrate is provided, including a plurality of light absorbing layers alternating between a layer of SiON and a layer of SiOand having a combined extinction coefficient &#x3e;0.5. As reflected light interacts with the light absorbing layers, a substantial amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches may be formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

Shallow trench isolation using antireflection layer

A method and apparatus for preventing contamination in a lithographic apparatus including a projection system, including providing the lithographic apparatus including the projection system for imaging an irradiated portion of a mask onto a target portion of a substrate and placing a pellicle over a surface of the projection system to inhibit contamination of the surface.

Pellicle for a lithographic lens

A phase-shifting mask for a photolithographic process includes a transparent material having first and second trenches. The first trench has a first depth and the second trench has a second depth deeper than the first depth. The phase-shifting mask is suitable for testing the effect of lights of two wavelengths on a layer of photoresist.

Method for using phase-shifting mask

Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a plurality of light absorbing layers having a combined extinction coefficient >0.5. As reflected light passes through the light absorbing layers, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

A method of fabricating a feature of an integrated circuit in a layer of material includes providing a layer of photoresist having a first thickness over the layer of material; forming apertures in the layer of photoresist; growing the layer of photoresist to a second thickness greater than the first thickness; and etching the layer of material through the apertures to fabricate a feature.

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Campbell, CA, United States of America

Carl P Babcock