A/n Inc.

Synopsys, Inc.

Nintendo Co., Ltd.

Nintendo of America Inc.

Arc International (uk) Limited

Carl Norman Graham

Peter R Warnes

Ben Cheese

Jeremy E San

Kar-Lik Kasim Wong

Simon James Jones

Aris Aristodemou

Yazid Nemouchi

Seow Chuan Lim

John R M Mason

Tim Hall

Methods and apparatus for adaptive encoding of data such as for example video data. In one exemplary embodiment, a real-time video encoder is disclosed that changes video encoding processes to produce the best quality encoded video while maintaining a target encoding frame rate, according to one or more operating constraints.

Adaptive video encoding apparatus and methods

A data path for a SIMD-based microprocessor is used to perform different simultaneous filter sub-operations in parallel data lanes of the SIMD-based microprocessor. Filter operations for sub-pixel interpolation are performed simultaneously on separate lanes of the SIMD processor's data path. Using a dedicated internal data path, precision higher than the native precision of the SIMD unit may be achieved. Through the data path according to this invention, a single instruction may be used to generate the value of two adjacent sub-pixels located diagonally with respect to integer pixel positions.

Systems and methods for accelerating sub-pixel interpolation in video processing applications

Inter-processor communication systems and methods that define within the instruction set of the microprocessor a command for directing the microprocessor to relinquish control over at least one of the microprocessor's internal registers. The microprocessor may then signal a communication interface that collects data from external sources. The communication interface takes control over the internal register released by the microprocessor and inputs the collected external data directly into the internal register of the microprocessor. Once data is place into the internal register, control of that register may be returned to the microprocessor.

Inter-processor communication method

Systems and methods for recording instruction sequences in a microprocessor having a dynamically decoupleable extended instruction pipeline. A record instruction including a record start address is sent to the extended pipeline. The extended pipeline thus begins recording the subsequent instruction sequence at the specified address until an end record instruction is encountered. The end record instruction is recorded as the last instruction in the sequence. The main pipeline may then call the instruction sequence by sending a run instruction including the start address for the desired sequence to the extended pipeline. This run instruction causes the extended pipeline to begin autonomously executing the recorded sequence until the end record instruction is encountered. This instruction causes the extended pipeline to cease autonomous execution and to return to executing instructions supplied by the main pipeline.

Microprocessor system and method for instruction-initiated recording and execution of instruction sequences in a dynamically decoupleable extended instruction pipeline

Two pairs of deblock instructions for performing deblock filtering on a horizontal row of pixels according to the H.264 (MPEG 4 part 10) and VC1 video codec algorithms. The first instruction of each pair has three 128-bit operands comprising the 16-bit components of a horizontal line of 8 pixels crossing a vertical block edge between pixelsandin a YUV image, a series of filter threshold parameters, and a 128-bit destination operand for storing the output of the first instruction. The second instruction of each pair accepts the same 16-bit components as its first input, the output of the first instruction as its second input and a destination operand for storing an output of the second instruction as its third input. The instruction pairs are intended for use with the H.264 or VC1 video codecs respectively.

System and methods for performing deblocking in microprocessor-based video codec applications

A video game system is described for use with a television type display device including a host video game system housing a game program processor and a programmable special purpose hardware graphics processor. The programmable graphics processor communicates with the host game processor and incorporates an embedded RAM cache memory. The programmable graphics processor has hardware circuitry for performing 3D geometry transformations such as a 3&#xd7;3 matrix transformation of x, y and z graphics data to provide 3D rotated and/or scaled polygon-based 3D graphic objects and also includes dedicated hardware for plotting individual pixels. The graphics coprocessor utilizes an instruction set that is designed to efficiently implement 3D matrix rotation and scaling operations associated with 3D graphics and also includes special instructions for plotting character-mapped pixels.

External memory system having programmable graphics processor for use in a video game system or the like

A fully programmable, graphics microprocessor is disclosed which is designed to be embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM. The fully user programmable graphics coprocessor has an instruction set which is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system's character mapped display which, from the programmer's point of view, creates a 'virtual' bit map by permitting the addressing of individual pixels&#x2014;even though the host system is character based. The graphics coprocessor interacts with the host coprocessor such that the graphics coprocessor's 16 general registers are accessible to the host processor at all times.

External memory system having programmable graphics processor for use in a video game system of the like

A fully programmable, graphics microprocessor is disclosed which is designed to be embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM. The fully user programmable graphics coprocessor has an instruction set which is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system's character mapped display which, from the programmer's point of view, creates a &ldquo;virtual&rdquo; bit map by permitting the addressing of individual pixels&mdash;even though the host system is character based. The graphics coprocessor interacts with the host coprocessor such that the graphics coprocessor's general registers are accessible to the host processor at all times.

Programmable graphics processor for use in a video game system or the like

A fully programmable, graphics microprocessor is embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM. The fully user programmable graphics coprocessor has an instruction set which is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system's character mapped display which, from the programmer's point of view, creates a 'virtual' bit map by permitting the addressing of individual pixels--even though the host system is character based. The graphics coprocessor interacts with the host coprocessor such that the graphics coprocessor's 16 general registers are accessible to the host processor at all times.

Growing community of inventors

London, United Kingdom

Carl Norman Graham