Intel Corporation

Agere Systems Inc.

Massana Research Limited

Lsi Corporation

Carl Murray

Elmoustapha Ould-Ahmed-Vall

Robert Valentine

Mark Jay Charney

Jesus Corbal

Venkateswara Rao Madduri

Philip Curran

Alberto Molina Navarro

Bret L Toll

Milind Baburao Girkar

Albert Molina

Kameran Azadet

Samer Lutfi Hijazi

Joseph H Othmer

Brian Paul Murray

Stephen Bates

Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate an unsigned fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

Instructions for vector multiplication of unsigned words with rounding

Embodiments of systems, apparatuses, and methods for performing vector-packed controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

Systems, apparatuses, and methods for controllable sine and/or cosine operations

Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate a signed fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

Instructions for vector multiplication of signed words with rounding

Disclosed embodiments relate to executing a vector unsigned multiplication and accumulation instruction. In one example, a processor includes fetch circuitry to fetch a vector unsigned multiplication and accumulation instruction having fields for an opcode, first and second source identifiers, a destination identifier, and an immediate, wherein the identified sources and destination are same-sized registers, decode circuitry to decode the fetched instruction, and execution circuitry to execute the decoded instruction, on each corresponding pair of first and second quadwords of the identified first and second sources, to: generate a sum of products of two doublewords of the first quadword and either two lower words or two upper words of the second quadword, based on the immediate, zero-extend the sum to a quadword-sized sum, and accumulate the quadword-sized sum with a previous value of a destination quadword in a same relative register position as the first and second quadwords.

Vector instructions for selecting and extending an unsigned sum of products of words and doublewords for accumulation

Embodiments of systems, apparatuses, and methods for performing controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

A search sphere-based linear block decoder is provided. A received vector, v, is decoded by computing a syndrome vector, S, corresponding to the received vector, v; (S=vH); obtaining a set of all possible error vectors, e, corresponding to the computed syndrome vector, S, wherein the set of all possible error vectors, e, is obtained from a pre-computed error table and has a specified maximum number of bit errors; calculating a set of all possible received vectors, x, based on the received vector, v, and the set of all possible error vectors, e; determining a k-bit code-vector x that is closest to the received vector, v; and determining an n-bit data-vector, d, associated with the k-bit code-vector x. The pre-computed error table can be generated by multiplying all possible error vectors by a Syndrome Matrix, to obtain all possible syndrome vectors associated with all possible error vectors.

Methods and apparatus for search sphere linear block decoding

In a 1000 BASE-T transceiver, a timing error detector (TED,) receives its inputs directly from the output of an ADC () and from a decision device (). Timing recovery is acquired in three stages: a non-decision directed (NDD) stage during which only the output of an ADC () are used for acquisition; a stage for acquiring the remote scrambler and predicting symbols; and a decision-directed (DD) stage during which locally predicted symbols are also used for acquisition. Because the timing error detector (TED,) does not take inputs from the FFE () there is no information about cable length, and so an input of gain from an AGC is used to indicate cable length.

Timing recovery in data communication circuits

Channel equalization in a 1000BASE-T receiver is performed by a fixed mode analog filtersuitable for the longest possible cable length, by a FFE (), and by a digital filter. The digital filter () has two sets of taps. One set is optimal for shorter cable lengths and so cancels adaptation for long cable lengths and assists operation of the analog filter. A decision block () selects an appropriate set of taps.

Channel equalization in data receivers

A Gigabit transceiver () has a receiver () and a transmitter (). There is an ADC () in the receiver () for each channel (A, B, C, D). The ADCs () oversample at a factor of 2. However the remainder of the digital circuitry and transmitter DACs () operate off half of the oversampling rate. In the receiver () fractionally spaced equalisers (FSES,) ensure that the optimum sampling phase is selected digitally. The invention avoids the need for a PLL in the receiver for each channel and associated interference and retiming problems.

Timing control in data receivers and transmitters

A cancellation system comprises a channel circuit () for each noise source, such as echo in a particular cable pair. There are only eighty taps per channel, in two blocks (n_echo_a, f_echo_a). Each block is preceded by a variable delay line comprising blocks of registers cascaded so that a delay value of 0 to 40 clock cycles can be chosen. The delay value is determined by determining an optimum position for each tap block. This is achieved by determining a maximum coefficient sum for a number of windows. Taps from other channels are used during training, so that there is a total of 160 taps for each channel during training to enable the optimum positions to be determined.

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Carl Murray