Motorola Corporation

Freescale Semiconductor,inc.

Carl Kyono

David Joseph Monk

Vida Ilderem Burger

Kun-Hin To

Pamela J Welch

Rainer Thoma

Wen Ling M Huang

Sushil Bharatan

Francis K Chai

Sharanda L Bigelow

A structure that reduces signal cross-talk through the semiconductor substrate for System-On-Chip (SOC) () applications, thereby facilitating the integration of digital circuit blocks () and analog circuit blocks () onto a single IC. Cross-circuit interaction through a substrate () is reduced by strategically positioning the various digital circuit blocks () and analog circuit blocks () in an isolated wells (), (), () and () over a resistive substrate (). These well structures (), (), (), and () are then surrounded with a patterned low resistivity layer () and optional trench region (). The patterned low resistivity region () is formed below wells () and () and functions as a low resistance AC ground plane. This low resistivity region () collects noise signals that propagate between digital circuit blocks () and analog circuit blocks ().

Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications

A lateral PNP is disclosed in which a substrate of a first conductivity type is used. On top of the substrate a buried region of a second conductivity type is formed. A lightly doped collector region is located above the buried region. The lateral PNP also includes a base region of a second conductivity type formed by a graded channel implant and a well region of a second conductivity type, the well region contacting the base region, the buried region and a base contact. Additionally, there are collector contacts and emitter contacts of a first conductivity type. The lightly doped collector region results in a large Early voltage and the base region provides for a high current gain.

Lateral PNP and method of manufacture

Growing community of inventors

Tempe, AZ, United States of America

Carl Kyono