Advanced Micro Devices Corporation

Ati Technologies Ulc

Creative Technology Corporation

Carl Kittredge Wakeland

Philip Ng

Thomas Craig Savell

Michael Mantor

Timour T Paltashev

Guhan Krishnan

Jiasheng Chen

Michael S Quimby

Alexander Lyashevsky

Daniel B Reents

Saikishore Reddipalli

Alexander J Branover

Benjamin Tsien

William Herz

Venkateswara Rao Madduri

Gabor Sines

Alfred C Hartmann

Mehdi Saeedi

Daniel P Mann

David Francis Tobias

Xiaojie He

Lloyd W Gauthier

Christopher T Weaver

James O Mergard

Al Hartmann

Ming L So

Keith G Hawkins

Thomas Daniel Perry

J Scott Fuller

Xiao Gang Zheng

Donald G Craycraft

James M Torrey

Faheem Hayat

Felix Ho

Joseph Scanlon

Hoon Quat Gek

Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.

Secure and power efficient audio data processing

Systems, apparatuses, and methods for performing adaptive audio mixing are disclosed. A trained neural network dynamically selects and mixes pre-recorded, human-composed music stems that are composed as mutually compatible sets. Stem and track selection, volume mixing, filtering, dynamic compression, acoustical/reverberant characteristics, segues, tempo, beat-matching and crossfading parameters generated by the neural network are inferred from the game scene characteristics and other dynamically changing factors. The trained neural network selects an artist's pre-recorded stems and mixes the stems in real-time in unique ways to dynamically adjust and modify background music based on factors such as game scenario, the unique storyline of the player, scene elements, the player's profile, interest, and performance, adjustments made to game controls (e.g., music volume), number of viewers, received comments, player's popularity, player's native language, player's presence, and/or other factors. The trained neural network creates unique music that dynamically varies according to real-time circumstances.

Adaptive audio mixing

Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

Low power and low latency GPU coprocessor for persistent computing

Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.

Aligning active and idle phases in a mixed workload computing platform

A computing device may be configured to output a digital audio stream to an audio playback system for rendering as sound over speakers. The sound may be sampled. Based at least in part on a quality of the sampled sound, the data rate of the digital audio stream may be reduced by reducing a sampling rate and/or by reducing a number of bits per sample. A reduced sampling rate may be determined based on a computed maximum sampling rate of the audio playback system, and/or a reduced number of bits per sample may be determined based on a computed maximum number of bits per sample of the audio playback system. The maximum usable sampling rate and maximum usable number of bits per sample may be determined based on an upper usable frequency within a frequency spectrum of the sampled sound.

Adjusting a data rate of a digital audio stream based on dynamically determined audio playback system capabilities

Embodiments of a signal processing system, a method, and fractionally modulated digital delay lines are generally described herein. Other embodiments may be described and claimed. In some embodiments, a fractional address is generated by adding a delay value to a fractional offset value, and input sample values are interpolated based on a fractional portion of the fractional address. A write operation may be performed to the integer portion of the fractional address for each sample period using the interpolated input sample values. Adjusted addresses may be generated when addresses are either skipped of duplicated.

Method and signal processing device to provide one or more fractional delay lines

A method and digital processor to process digital samples is provided. The processor may comprise a time domain processing engine to process a digital sample in the time domain, and a frequency domain processing engine to process a digital sample in the frequency domain. Shared memory is provided in the digital processor with which time domain and frequency domain processed samples are exchangeable. The time domain processing engine may processes data samples in a sample-by-sample manner and the frequency domain processing engine may processes data samples in a block-based manner. The processing engines may be integrated in a single DSP chip. In one embodiment, an interrupt generator is provided that generates an interrupt and an input buffer communicates an input data sample to the processor in response to the interrupt and the output buffer communicates an output data sample to the digital sample bus in response to the interrupt.

Method and device to process digital media streams

A communication protocol processor is presented including a transmit unit and a receive unit, each having multiple microprocessor cores connected in series. Each microprocessor core performs an operation upon a stream of communication data, conducted along a data path, according to instructions and associated data stored within a code memory unit. A change in the operation performed by a given microprocessor core is effectuated during communication protocol processor operation by transmitting new instructions and associated data to the microprocessor core along the data path. The new instructions and data modify the existing instructions and associated data stored within the code memory unit. The transmit unit of the communication protocol processor receives packet (i.e., transmit) data in parallel units and produces a framed serial transmit data stream. Each microprocessor core of the transmit unit is assigned one or more tasks which must be accomplished in sequence in order to encapsulate the transmit data stream into frames in accordance with a selected communication protocol. The receive unit receives a framed serial receive data stream and produces packet (i.e., receive) data in parallel units. Each microprocessor core of the receive unit is assigned one or more tasks which must be accomplished in sequence in order to extract receive data from the framed serial receive data stream in accordance with the selected communication protocol. The communication protocol processor may be included within a microcontroller, and the microcontroller employed within a network interface unit (NIU).

Communication protocol processor having multiple microprocessor cores connected in series and dynamically reprogrammed during operation via instructions transmitted along the same data paths used to convey communication data

A delay line circuit and method to delay digital data in a main memory is provided. The delay line circuit may comprise primary delay line cache, secondary delay line cache, and a cache controller to control communication of data between the secondary delay cache and the primary delay cache. The primary delay line cache may receive digital data to be delayed from a signal processor module, and secondary delay line cache may be connected to the primary delay line cache and the main memory to send data to and receive delayed data from the main memory. Data in the secondary delay line cache may be updated with data from the main memory or with data from the primary delay line cache. The invention extends to a machine-readable medium comprising a set of instructions for executing any of the methods described herein.

Method and circuit to implement digital delay lines

A method for determining a position of a joystick in data communication with a processor and having an initial state that includes steps of varying the initial state in response to a signal from the processor; returning the joystick to the initial state after a duration of time, with the duration of time being dependent upon the position amongst a plurality of positions. A plurality of poll operations of the joystick are executed to sense the returning step. Each of the polling operations results in a data signal being transferred from the joystick indicating the state of the same, with consecutive poll operations being separated by a predetermined segment of time, defining a first interval and consecutive data signals operations being separated by a time period, defining a second interval. The second interval is increased to be greater than the first interval, the duration of time is measured by determining a number of data signals received by the processor between the varying step and the returning step. Thereafter, the spatial position of the joystick is determined.

Speed-compensated joystick

A microcontroller is presented having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface. The microcontroller includes a central processing unit (CPU), a first set of I/O pads, and a configurable logic block (CLB) all formed upon a single monolithic semiconductor substrate. The CPU is configured to execute instructions, preferably x86 instructions. The CPU produces CPU output signals during instruction execution. The CLB is coupled between the CPU output signals and the first set of I/O pads, and is configurable to perform a logic function selected from a predefined set of logic functions. Each member of the set of logic functions has an associated hardware interface including a signal table which defines a correspondence between CLB input/output signals and members of the first set of I/O pads. The microcontroller also preferably includes a test/program core coupled to a second set of I/O pads and to the CLB. The test/program core produces programming signals in response to signals received via the second set of I/O pads. The programming signals cause the CLB to perform the selected logic function. When programmed, the CLB produces CLB output signals in response to the CPU output signals. Each of the CLB output signals is coupled to one or more of the members of the first set of I/O pads according to the hardware interface of the selected logic function.

Microcontroller having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface

A processor-based device incorporating a software debug port that utilizes a JTAG or similar standardized interface, thereby providing a software debug communication mechanism that does not require a special bond-out package. In one embodiment of the invention, only standard JTAG pins are used for communications between a host platform and a target system incorporating a target processor. In another embodiment of the invention, the software debug port of the target processor is augmented for higher-speed access via optional sideband signals. When used in conjunction with an on-chip trace cache, the software debug port provides trace information for reconstructing instruction execution flow on the processor and is also capable of examining register contents without halting processor operation. The software debug port alleviates many of the packaging and clock synchronization problems confronting existing debug solutions.

Software debug port for a microprocessor

Growing community of inventors

Scotts Valley, CA, United States of America

Carl Kittredge Wakeland