Transphorm Technology, Inc.

Transphorm Inc.

University of California

Carl Joseph Neufeld

Umesh Kumar Mishra

Rakesh K Lal

David Michael Rhodes

Geetak Gupta

Mo Wu

Srabanti Chowdhury

Ilan Ben-Yaacov

Brian L Swenson

Davide Bisi

Steven P DenBaars

Toshihide Kikkawa

Stacia Keller

Likun Shen

John Kirk Gritters

Xiang Liu

Ronald Avrom Barr

An electronic component includes at least three terminals extending from a component package. The component includes a depletion-mode III-N transistor, and an enhancement-mode transistor in the package. A gate electrode of the enhancement-mode transistor is electrically connected to the first terminal, a source electrode of the enhancement-mode transistor and a gate electrode of the depletion-mode III-N transistor are electrically connected to the second terminal, a drain electrode of the enhancement-mode transistor is electrically connected to a source electrode of the depletion-mode III-N transistor, and a drain electrode of the depletion-mode III-N transistor is electrically connected to the third terminal. The drain electrode includes multiple drain pads each sequentially a further distance from the third terminal, where a wire-bond extends from each drain pad to the third terminal, each wire-bond having a length, where a diameter of the longest wire-bond is greater than the diameter of the shortest wire-bond.

III-N devices with improved reliability

A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.

Lateral III-nitride devices including a vertical gate module

A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous AlSiO layer with 0.2&#x3c;x&#x3c;0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.

Enhancement mode III-nitride devices having an Al-SiO gate insulator

A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.

III-nitride devices including a graded depleting layer

A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.

Forming enhancement mode III-nitride devices

An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.

N-polar III-nitride transistors

A method of fabricating a heterostructure device, including (a) obtaining a first layer or substrate; (b) growing a second layer on the first layer or substrate; and (c) forming the second layer that is at least partially relaxed wherein (1) the first layer and the second layer have the same lattice structure but different lattice constants, (2) the first layer and the second layer form a heterojunction, and (3) the heterojunction forms an active area of a device or serves as a pseudo-substrate for the device.

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Goleta, CA, United States of America

Carl Joseph Neufeld