International Business Machines Corporation

Stmicroelectronics Gmbh

Other

Globalfoundries Inc.

Infineon Technologies Ag

Adeia Semiconductor Bonding Technologies Inc.

Infineon Technologies North America Corp.

Siemens Aktiengesellschaft

Siemens Aktiengesell Schaft

Infineon Technologies LLC

Adeia Semiconductor Solutions LLC

Siemens Microelectronics Limited

Qimonda Ag

Carl John Radens

Lawrence Alfred Clevenger

Jack Allan Mandelman

Kangguo Cheng

Ramachandra Divakaruni

John H Zhang

Louis L Hsu

Timothy Joseph Dalton

William R Tonti

Ruilong Xie

Chih-Chao Yang

Gary Bela Bronner

Juntao Li

Jeffrey P Gambino

Bruce Bennett Doris

Dureseti Chidambarrao

Keith Kwong Hon Wong

Louis C Hsu

Junli Wang

Li-Kong Wang

Oleg Gluschenkov

Kevin Shawn Petrarca

Richard Quimby Williams

Rajiv V Joshi

Michael Patrick Chudzik

Omer H Dokumaci

Toshiharu Furukawa

Dechao Guo

Geng Wang

Rajarao Jammy

Chandrasekhar Narayan

Michael C Gaidis

Herbert Lei Ho

Arvind Kumar

Hsueh-Chung Chen

Albert Manhee Chu

Brent A Anderson

Sampath Purushothaman

Elbert Emin Huang

Zhengwen O Li

Anthony K Stamper

Veeraraghavan S Basker

Julien Frougier

Richard Stephan Wise

Louis Lu-Chen Hsu

Thomas W Dyer

Huilong Zhu

Ravikumar Ramachandran

Dirk Pfeiffer

Unoh Kwon

Terry Allen Spooner

Siddarth A Krishnan

John Kenneth DeBrosse

Sani Richard Nassif

Jochen C Beintner

Harold John Hovel

Roger Allan Quon

Alexander Reznicek

Devendra K Sadana

David V Horak

Ghavam G Shahidi

Chung H Lam

Chen Zhang

Theodorus E Standaert

Robert J Gauthier, Jr

Vijay Narayanan

Mukta G Farooq

James William Adkisson

Praneet Adusumilli

Oscar Van Der Straten

Matthew Earl Colburn

Yann Mignot

Kisik Choi

Babar Ali Khan

Jente Benedict Kuang

Tze-Chiang Chen

Helmut Horst Tews

Steven J Bentley

Ahmet Serkan Ozcan

Conal Eugene Murray

Wagdi William Abadeer

Kiran V Chatty

Jeffrey Scott Brown

Ali Khakifirooz

Nicolas J Loubet

Jingyun Zhang

Zuoguang Liu

Christopher Vincent Jahnes

Su Chen Fan

Laertis Economikos

Till Schloesser

Wayne Frederick Ellis

Pranita Kerber

Stephen Victor Kosonocky

Robert C Wong

Jon Alfred Casey

Indira P Seshadri

Dae-Gyu Park

John Christopher Arnold

Johnathan E Faltermeier

A semiconductor structure is provided that includes a second nanosheet device of a second conductivity type stacked over a first nanosheet device of a first conductivity type that is different from the second conductivity type. Each of the first and second nanosheet devices includes at least one semiconductor channel material nanosheet. One side of the least one semiconductor channel material nanosheet of both the first and second nanosheet devices contacts a dielectric material, while another side of the least one semiconductor channel material nanosheet of both the first and second nanosheet devices contacts a functional gate-containing liner that extends laterally to connect to a gate contact of each first and second nanosheet device.

CFET with independent gate control and low parasitic capacitance

According to the embodiment of the present invention, a semiconductor device includes a first nanodevice and a second nanodevice. The second nanodevice is located adjacent to and parallel to the first nanodevice along a first axis. The first nanodevice and the second nanodevice each include a first section, a second section, and a third section. A first gate cut region is located between the first sections of the first nanodevice and the second nanodevice. A middle gate cut region is located between the second sections of the first nanodevice and the second nanodevice. A third gate cut region is located between the third sections of the first nanodevice and the second nanodevice. The middle gate cut region has different dimensions along a second axis than the first gate cut region and the third gate cut region.

Different dimensions across active region for stronger via to backside power rail

A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a first stacked field effect transistor (FET) structure in a first device area, the first stacked FET structure comprising a first pull down (PD) transistor, and a first pull up (PU) transistor disposed over the first PD transistor, a first metal gate that is shared by the first PD transistor and the first PU transistor; and an oxygen blocking layer provided on the first metal gate.

Static random access memory device with stacked FETs

A phase change memory includes a phase change structure. There is a heater coupled to a first surface of the phase change structure. A first electrode is coupled to a second surface of the phase change structure. A second electrode coupled to a second surface of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode connected to a second lateral end of the phase change structure.

Multi-level programming of phase change memory device

A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside power rail.

Local enlarged via-to-backside power rail

A semiconductor memory cell comprising six vertical-transport field-effect transistors (VTFET) on a wafer. The six VTFET are in a first layer. The six VTFET are in a first row.

High density static random-access memory

A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

Metal lines with low via-to-via spacing

A stacked phase change memory structure having a cross-point architecture is provided. The stacked phase change memory structure includes at least two phase change material element-containing structures stacked one atop the other. Each phase change material element-containing structure of the plurality of phase change material element-containing structures has a cross-point architecture and includes, from bottom to top, at least one bottom electrode, a phase change material element, and a top electrode.

Stacked cross-point phase change memory

A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

Forming self-aligned vias and air-gaps in semiconductor fabrication

An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.

Electronic devices with a low dielectric constant

Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.

Hybrid gate cut for stacked transistors

A stacked layer memory for a SRAM includes a first layer of the SRAM, including multiple transistors of a first type, and includes a second layer of the SRAM, having multiple transistors of a second type. The first and second layers are different layers stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type. A method for forming the stacked layer memory for the SRAM includes forming the first layer and the second layer. The first and second layers are different layers and are formed to be stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first and second types.

Stacked layer memory suitable for SRAM and having a long cell

Embodiments described herein provide for integrated input/output and logic devices for nanosheet technology and methods of fabrication for the devices. The types of transistors used for input/output devices and logic devices may differ such that, for example, input/output devices may use EG (Extended Gate) Field Effect Transistors (FET) while logic devices may use Suspended Gate (SG) FETs. Co-locating SG and EG devices on a single die provides for a fabricator to assure alignment between the nanosheets used in the SG and EG devices (improving consistency in the device characteristics on a single die) and reduce overall space requirements for the hardware used by input/output and logic devices.

Integrated input output and logic device for nanosheet technology

A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

Stacked FET SRAM

A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

Replacement gate cross-couple for static random-access memory scaling

Growing community of inventors

Lagrangeville, NY, United States of America

Carl John Radens