International Business Machines Corporation

Stmicroelectronics Gmbh

Other

Globalfoundries Inc.

Infineon Technologies Ag

Adeia Semiconductor Bonding Technologies Inc.

Infineon Technologies North America Corp.

Siemens Aktiengesellschaft

Infineon Technologies LLC

Siemens Aktiengesellshaft

Siemens Microelectronics Limited

Carl John Radens

Lawrence Alfred Clevenger

Jack Allan Mandelman

Kangguo Cheng

Ramachandra Divakaruni

John H Zhang

Louis L Hsu

Timothy Joseph Dalton

William R Tonti

Chih-Chao Yang

Gary Bela Bronner

Ruilong Xie

Jeffrey P Gambino

Juntao Li

Bruce Bennett Doris

Dureseti Chidambarrao

Keith Kwong Hon Wong

Louis C Hsu

Li-Kong Wang

Junli Wang

Oleg Gluschenkov

Kevin Shawn Petrarca

Richard Quimby Williams

Rajiv V Joshi

Michael Patrick Chudzik

Omer H Dokumaci

Toshiharu Furukawa

Dechao Guo

Geng Wang

Rajarao Jammy

Chandrasekhar Narayan

Michael C Gaidis

Herbert Lei Ho

Arvind Kumar

Hsueh-Chung Chen

Sampath Purushothaman

Elbert Emin Huang

Zhengwen O Li

Albert Manhee Chu

Anthony K Stamper

Brent A Anderson

Veeraraghavan S Basker

Julien Frougier

Richard Stephan Wise

Louis Lu-Chen Hsu

Thomas W Dyer

Huilong Zhu

Ravikumar Ramachandran

Dirk Pfeiffer

Unoh Kwon

Terry Allen Spooner

Siddarth A Krishnan

John Kenneth DeBrosse

Sani Richard Nassif

Jochen C Beintner

Harold John Hovel

Roger Allan Quon

Alexander Reznicek

Devendra K Sadana

David V Horak

Ghavam G Shahidi

Chung H Lam

Theodorus E Standaert

Robert J Gauthier, Jr

Vijay Narayanan

Mukta G Farooq

James William Adkisson

Praneet Adusumilli

Oscar Van Der Straten

Matthew Earl Colburn

Yann Mignot

Babar Ali Khan

Kisik Choi

Jente Benedict Kuang

Tze-Chiang Chen

Helmut Horst Tews

Steven J Bentley

Conal Eugene Murray

Ahmet Serkan Ozcan

Wagdi William Abadeer

Kiran V Chatty

Jeffrey Scott Brown

Ali Khakifirooz

Chen Zhang

Nicolas J Loubet

Jingyun Zhang

Zuoguang Liu

Christopher Vincent Jahnes

Su Chen Fan

Laertis Economikos

Till Schloesser

Wayne Frederick Ellis

Pranita Kerber

Stephen Victor Kosonocky

Robert C Wong

Jon Alfred Casey

Dae-Gyu Park

Indira P Seshadri

Johnathan E Faltermeier

John Christopher Arnold

A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside power rail.

Local enlarged via-to-backside power rail

A semiconductor memory cell comprising six vertical-transport field-effect transistors (VTFET) on a wafer. The six VTFET are in a first layer. The six VTFET are in a first row.

High density static random-access memory

A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

Metal lines with low via-to-via spacing

A stacked phase change memory structure having a cross-point architecture is provided. The stacked phase change memory structure includes at least two phase change material element-containing structures stacked one atop the other. Each phase change material element-containing structure of the plurality of phase change material element-containing structures has a cross-point architecture and includes, from bottom to top, at least one bottom electrode, a phase change material element, and a top electrode.

Stacked cross-point phase change memory

An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.

Electronic devices with a low dielectric constant

Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.

Hybrid gate cut for stacked transistors

A stacked layer memory for a SRAM includes a first layer of the SRAM, including multiple transistors of a first type, and includes a second layer of the SRAM, having multiple transistors of a second type. The first and second layers are different layers stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type. A method for forming the stacked layer memory for the SRAM includes forming the first layer and the second layer. The first and second layers are different layers and are formed to be stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first and second types.

Stacked layer memory suitable for SRAM and having a long cell

Embodiments described herein provide for integrated input/output and logic devices for nanosheet technology and methods of fabrication for the devices. The types of transistors used for input/output devices and logic devices may differ such that, for example, input/output devices may use EG (Extended Gate) Field Effect Transistors (FET) while logic devices may use Suspended Gate (SG) FETs. Co-locating SG and EG devices on a single die provides for a fabricator to assure alignment between the nanosheets used in the SG and EG devices (improving consistency in the device characteristics on a single die) and reduce overall space requirements for the hardware used by input/output and logic devices.

Integrated input output and logic device for nanosheet technology

A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

Stacked FET SRAM

A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

Replacement gate cross-couple for static random-access memory scaling

A structure including a bottom electrode on a substrate, a first side electrode vertically aligned above the bottom electrode, a set of alternating layers of insulator layers and conductive layers horizontally adjacent to the first side electrode, and a resistance switching material layer, the resistance switching material layer horizontally adjacent to a first side of the set of alternating layers. A method including forming a structure, the structure including alternating layers of insulator layers and conductive layers on a substrate, the substrate including a bottom electrode, removing a vertically aligned portion of the alternating layers forming a first trench, forming a first side electrode adjacent to the alternating layers in a portion of the first trench, removing another vertically aligned portion of the alternating layers forming a second trench, and forming a resistance switching material layer in the second trench.

Memory cell with comb-shaped electrodes

Embodiments of present invention provide a SRAM memory. The SRAM memory includes a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; a frontside cross-couple at the frontside, above the first and second PU transistors, that connects a first source/drain (S/D) region of the first PU transistor with a gate of the second PU transistor; and a backside cross-couple, at the backside underneath the first and second PD transistors, that connects a first S/D region of the second PD transistor with a gate of the first PD transistor. A method of manufacturing the SRAM memory is also provided.

SRAM with backside cross-couple

A phase-change memory device includes a bottom electrode; a stack of alternating electrical conductor layers directly contacting a top surface of the bottom electrode; a metal pillar directly contacting a top surface of the stack; a phase change material element directly contacting a top surface of the metal pillar; and a top electrode on the phase change material element, wherein a lateral dimension of the metal pillar is smaller than that of the stack.

Phase change memory cell having pillar bottom electrode with improved thermal insulation

Provided is a reconfigurable Ring Oscillator (RO) Physical Unclonable Function (PUF), which comprises a NAND gate with a first input line and a second input line and a series of inverters with at least one memory cell placed between two inverters of the series of inverters, where an output of a last inverter provides input to the second input line, and where the memory cell comprises a Field Effect Transistor (FET). In addition, the reconfigurable RO PUF comprises a frequency counter, where the output of the last inverter provides input to the frequency counter. In normal operation mode, the first input line is on to enable ring oscillation and the FET is off. In reconfiguration mode, the first input line is off and the FET is on to enable reconfiguration.

Reconfigurable ring oscillator (RO) physical unclonable function (PUF)

A ring-shaped heater, system, and method to gradually change the conductance of the phase change memory through a concentric ring-shaped heater. The system may include a phase change memory. The phase change memory may include a bottom electrode. The phase change memory may also include a ring-shaped heater patterned on top of the bottom electrode, the ring-shaped heater including: a plurality of concentric conductive heating layers, and a plurality of insulator spacers, where each insulator spacer separates each conductive heating layer. The phase change memory may also include a phase change material proximately connected to the ring-shaped heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

Phase change memory with concentric ring-shaped heater

Growing community of inventors

Lagrangeville, NY, United States of America

Carl John Radens