3com Corporation

International Business Machines Corporation

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP (singapore) Pte. Ltd.

Emulex Design & Manufacturing Corporation

Emulex Corporation

Carl John Lindeborg

James Scott Hiscock

James B Williams

John Ernest Ziegler

David James Duckman

Shawn Adam Clayton

James Winston Smart

Maria Clara Gutierrez

William Irving Leavitt

John Leland Wood

Alexander Nicolson, Iv

David Stoner

James L Moran

Anthony D Walker

Bradley S Trubey

Robin Lee Brown

David E Bartolini

John Griesing

Normand Louis Magnan

Liz Lindell

Edward Carroll

Sudhir Srinivasan

Glenn A Dearth

Hsiang-Tsung Kung

James Duda

David James Mannion

Norm Magnan

Jonnavithula Sreekanth

Mark David Moreau

Keith Louis Petry

A system for enabling input/out virtualization for a device is disclosed. In one embodiment the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Inline PCI-IOV adapter

A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

A hierarchically-organized linked list structure have a first level comprised of sections of sequentially-ordered segments, and a second level comprised of representatives of each of said sections at the first level. A method for maintaining the hierarchically-organized linked list structure to facilitate segment insertion, retrieval and removal.

Structure and method for maintaining ordered linked lists

In a digital data processing system having a memory component, a structure and method for managing available memory resources. Free pointers to respective free memory blocks are stored in memory blocks maintained as a linked list. In a system having a hierarchically-organized memory component, a small number of the free pointers are maintained at a relatively higher performance level of the memory and the balance of the free pointers are maintained at a relatively lower performance level of the memory.

Structure and method for managing available memory resources

A system and method are disclosed for detecting and preventing bridge loops in a relatively low cost bridge module designed for installation in a network hub. The bridge operates to monitor an intra-hub communication path of the network hub to detect bridge protocol data units transmitted by a switching fabric within the network hub. The bridge module stores a MAC source address of a bridge protocol data unit detected on the intra-hub communications path, and forwards the bridge protocol data unit through its external communication ports to respective network segments. The bridge module monitors its external communication ports for any data unit having a destination address matching a bridge multicast address. When a data unit having a destination address matching the bridge multicast address is detected, the bridge module compares the MAC source address of that data unit to the previously stored MAC source address from the bridge protocol data unit detected on the intra-hub communication path. In the event that the MAC source address of the data unit detected on the external communication port matches the previously stored MAC source address, the bridge module disables operation of the respective one of its external communication ports at which the data unit was received. In one embodiment of the disclosed system, the bridge module further monitors its external communications ports for routing protocol messages. In the event that a routing protocol message is detected on one of those external communications ports, the bridge module disables that port.

Intelligent network topology and configuration verification using a method of loop detection

A computer network switch includes a receiving module for receiving packets, a packet memory with a plurality of buffer cells with each of the buffer cells having a buffer descriptor. A descriptor free pool lists available buffer descriptors that can be used for new incoming packets. A plurality of transmit queues hold the buffer descriptors. Each of the transmit queues include an input queue, an expansion queue and an output queue. The switch also includes control logic for directing the removing of one of the available buffer descriptors from the free pool and directing one of the packets from the receiving module into one of the buff cells corresponding to the one available buffer descriptor. The control logic places the one buffer descriptor in the input queue of one of the transmit queues. The control logic also monitors a load status of the input and output queues.

Transmit queue caching

A main data memory is provided in a network device and includes a plurality of buffers for storing data packets. A plurality of descriptors, or pointers, point to the individual buffers. A status of the descriptors is stored in a descriptor reference memory. The status information includes whether the descriptors are in an active or free state, and an indication of copies of the descriptors in the transmit queues. A descriptor free pool includes a list of the descriptors in the free state.

Method and apparatus for detecting duplicate buffers in a descriptor based multi-port queue

Method and apparatus to detect lost buffers with a descriptor based queue

A switch of a computer network with a plurality of dual speed Ethernet client ports and at least one high speed Ethernet uplink port. The combined data rate of the Ethernet dual speed client ports has a maximum value which is higher than the data rate of the Ethernet uplink port. The Bandwidth Control limits the number of enabled Ethernet client ports so that the combined data rate of the enabled client ports substantially equals, or slights exceeds the data rate of the uplink port. In this way the speed and amount of switch memory can be minimized in the switch itself and the memory burden is divided among the clients. The dividing of the memory burden greatly reduces the worst case scenario and allows each client to individually chose the speed and amount of memory based on its own cost/benefit situation.

Method and apparatus for bandwidth control in an over subscribed

A LAN to ATM switch module includes a memory with an ATM port, a LAN port and a processor port. Each of port separately reading and writing information to/from the memory. An ATM interface is included for reading information from the ATM port and converting the information into an ATM format. The ATM interface also converts ATM format information to be delivered to the ATM port and written to the memory. A LAN interface reads information from the LAN port and converts the information into LAN format. The LAN interface also converts LAN information from a LAN packet channel bus to the LAN port, to be written to the memory. The switch module also includes a processor for reading information in the memory through the processor port. The processor determines the processing need for the information, the processor modifies the information in the memory according to the processing needed by writing to the memory through the processor port and controlling the ATM and LAN interfaces according to the processing needed.

LAN to ATM backbone switch module

A multiport or multiported memory device is provided. A first user and at least a second user are provided. A multilevel memory arbitration system is implemented which establishes arbitration cycles wherein the high priority user is granted priority as to access either during each arbitration cycle or during a greater number of arbitration cycles. A source burst limiter is provided associated with the high priority user. The source burst limiter monitors access of the high priority user to the multiport memory and limits such access based on a comparison of access attributes to some access attribute threshold.

Multiported memory access system with arbitration and a source burst

A token ring network performs address to port mapping by taking advantage of the abilities of the port switched modules and the neighbor notification process, in order to perform address to port mapping on each individual module. Ring monitors are switched from an upstream side of a port to a downstream side of a port when the neighbor notification process enters the port domain. The processor on the module records all the addresses received on the downstream side of the port, when the neighbor notification process is in the domain of that port. If it appears that the neighbor notification process is in the domain of two adjacent ports, the present invention only records addresses from the most downstream of the two adjacent ports, since such a situation is an indication that the upstream ports do not conform to MAC protocol. If a non-protocol station is connected to the last port in a module, the module will collect addresses from that port until the neighbor notification process enters the most upstream port of the module. At that point, addresses are no longer recorded in the most downstream port, and each set of addresses for each port are checked to determine if the last entry in each port has the ARI bits set to one and the source address is similar to the address of the most upstream neighbor of the module. If the addresses are the same, all addresses recorded in that port are ignored, since that port contains a non-protocol station.

Method and apparatus for address to port mapping in a token ring network

Beacon recovery is performed separately on each module. After a module recognizes that a beacon condition has occurred, each module checks to determine if the defect or fault is on its module. If the defect is on the respective module, the module disconnects itself from the remaining modules in the network and transmits a beacon frame onto an upstream end of the group of stations on that module. Each port on the module is then tested to determine if the error lies in the corresponding station. This testing is based on the presence or absence of the beacon frame.

Method and apparatus for correcting a defect in a token ring network

Growing community of inventors

Shrewsbury, MA, United States of America

Carl John Lindeborg