Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Nxp B.v.

Philips Semiconductors Inc.

Crocus Technology Inc.

Carl J Knudsen

Ken Jaramillo

A tamper-resistant packaging approach protects an integrated circuit () from undesirable access. According to an example embodiment of the present invention, data is encrypted as a function of the state of a plurality of magnetically-responsive circuit elements (-) and then decrypted as a function of the state (-). A package () is arranged to prevent access to the integrated circuit and having magnetic particles (-) therein. The magnetic particles (-) are arranged to cause the magnetically-responsive circuit elements (-) to take on a state that is used to encrypt the data. The state of these elements is again accordingly used to decrypt the data (e.g., as a key). When the magnetic particles are altered, for example, by removing a portion of the package, the state of one or more of the magnetically-responsive circuit elements is changed, thus rendering the state incapable of being used for decrypting the data.

Tamper-resistant packaging and approach using magnetically-set data

A tamper-resistant packaging approach protects non-volatile memory. According to an example embodiment of the present invention, an array of magnetic memory elements (-) in an integrated circuit () are protected from magnetic flux() by a package () including a magnet (). Flux from the magnet is directed away from the magnetic memory elements by the package. When tampered with, such as by removal of a portion of the package for accessing the magnetic memory elements, the package allows the flux to reach some or all of the magnetic memory elements, which causes a change in a logic state thereof. With this approach, the magnetic memory elements are protected from tampering.

Tamper resistant packaging and approach

A circuit arrangement reduces the number of interrupts to a DSP required to transfer digital samples between external I/O devices and a data memory, thus allowing the DSP to perform additional sample processing operations. An interrupt accelerator responds to I/O interrupts from an I/O device by pausing the DSP, transferring samples with the data memory, and tracking the number of samples transferred. When a predetermined number of samples have been transferred, the interrupt accelerator interrupts the DSP to perform a block transfer of samples in conjunction with sample processing.

Method and system for an interrupt accelerator that reduces the number of interrupts for a digital signal processor

The present invention comprises a smart retry system for agents in a computer system. The smart retry system of the present invention includes a master agent, a slave agent, an arbiter, and smart retry logic components, all adapted to be coupled to a bus. The bus permits agents coupled to the bus to communicate with the arbiter and other agents coupled to the PCI bus. The smart retry logic component of the present invention prevents a PCI master agent from accessing the bus for the purpose of attempting a retry transaction, until after the slave agent that issued the retry is ready.

Smart retry system that reduces wasted bus transactions associated with master retries

A reverberation processor and method for generating reverberation in a digital audio processing system. The reverberation processor uses register files programmed with tap page and tap offset addresses to gather the audio data for the reverberation taps. The address of each block transferred is determined by the tap number, which selects an offset register to provide a lower portion of the address, and the page number which selects a page register to provide the upper portion of the address. Control logic provides for enabling of the address and initiation of transfers to and from memory on a bus. Dual port register files are used to receive that data for a digital signal processor (DSP). The DSP computes a reverberation result and fills another dual port register file. The register files signal the control logic to initiate transfers when the input data drops below a threshold or the output data exceeds a threshold. The register files are pre-loaded so that block transfers from each tap are staggered in time and no two transfers occur in any one sample period.

Digital reverberation processor and method for generating digital reverberation

The present invention comprises a system for implementing pseudo delayed transactions through a bridge in order to guarantee access to a shared device. The system of the present invention functions in a computer system having a plurality of busses, including a first bus on one side of a bridge and a second bus on another side of the bridge. A first initiator device and a second initiator device are coupled to the first bus. The first and second initiator devices are both adapted to request ownership of the first bus and receive a respective first and second grant signal responsive thereto. A target device is coupled to the second bus. The bridge is coupled to the first bus and the second bus. The bridge is adapted to implement data transactions between the target device and the first device or the second device. The bridge is further adapted to support a pseudo delayed transaction for the first or second device, wherein the pseudo delayed transaction is supported without requiring the storage of address or command/byte enable information, such that the first and second device are both guaranteed access to the target device.

Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource

A system is delineated comprising, in combination, an integrated circuit having N internal masters coupled to a buried, internal bus, and register circuitry coupled to the buried, internal bus and having an output providing status data for each of the N internal masters. The output from the register circuitry is directly coupled to a processor for permitting the processor to monitor request and grant status for each internal master, thereby allowing the processor to keep track of which, if any, of the internal masters attempt to 'hog' the internal, buried bus. Additionally, the processor can set enabling registers located in the register circuitry to one value for permitting properly operating internal masters to have access to the internal, buried bus, and to another value to disable one or more 'hogging' internal masters from accessing the internal, buried bus. The system further includes N external devices coupled, on a one-to-one basis, to the N internal masters.

Growing community of inventors

Gilbert, AZ, United States of America

Carl J Knudsen