International Business Machines Corporation

Carl J Anderson

Michael Stephen Floyd

Phillip John Restle

Kevin Franklin Reick

Mark B Ketchen

Manjul Bhushan

Albert X Widmer

Norman Karl James

Larry Scott Leitner

Bradley David McCredie

John Farley Ewen

Brian Chan Monwai

Jennifer Lane Vargus

Kevin R Wrenner

Sensors on the integrated circuit are used to detect the current operating state of the chip, such as frequency, voltage, temperature characteristics, or variation in the integrated circuit manufacturing process. In response, the integrated circuit may choose to modify operational parameters (such as frequency, voltage, or power-down states) in order to dynamically and autonomously maintain an optimal performance and/or power-efficiency operational point.

Self-learning of the optimal power or performance operating point of a computer chip based on instantaneous feedback of present operating environment

A method and system for dynamic characterization observability using functional clocks for system or run-time process characterization. Silicon characterization circuitry may be read after silicon chips have been assembled in a package and installed in a system. A characterization circuit comprising one or more oscillators generates signal pulses, wherein the signal pulses represent a frequency of a circuit in the processor chip. A sampler circuit is connected to the characterization circuit, wherein the sampler circuit counts the number of the signal pulses from the characterization circuit within a predetermined time period. A control unit is connected to the sampler circuit, wherein the control unit comprises macros for collecting count data from the one or more oscillators to determine the silicon characterization. Based on the silicon characterization, the optimal operating frequency of the processor chip may be identified, as well as possible lifetime degradation of circuits on the chip.

Dynamic silicon characterization observability using functional clocks for system or run-time process characterization

A method of characterizing a circuit comprises the steps of measuring a first delay associated with the circuit when the circuit is substantially unloaded; measuring a second delay associated with the circuit when the circuit is loaded by a predetermined impedance; determining a difference between the second delay and the first delay, the delay difference corresponding to a switching impedance associated with the circuit; and determining a characterization parameter of the circuit, the characterization parameter being a function of at least the switching impedance associated with the circuit. The methodologies of the present invention are directed primarily to individually evaluating pullup and pulldown delays with substantial precision (e.g., sub-picosecond) for a representative set of circuits in the presence of an arbitrary switching history.

Method and apparatus for characterizing a circuit with multiple inputs

A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with the selectively recorded data output, such that the integrated circuit is tested by subsets, independently of testing the integrated circuit in its entirety.

Method and system for performing pseudo-random testing of an integrated circuit

Boat hull

The present invention is a fully integrated digital filter which interacts with a phase comparator to provide a phase lock loop and data retiming function. The digital filter includes a prescaler, a six bit reversible counter, and a four bit reversible counter. The phase comparator is a D-type edge-triggered flip-flop in which an input data signal clocks the flip-flop and samples a clock signal to determine whether the clock signal leads or lags the input data signal. The clock signal is repeatedly sampled and the digital filter counts the number of leading and lagging signals. The digital filter counts the leading and lagging signals in groups so that the counting rate of the digital filter does not have to be as high as the input data rate. The prescaler groups the bits and the six bit counter determines the number of samples that indicate a clock lead or lag. The output of the six bit counter is the input to a four bit counter which provides a digital signal that controls the relative phase difference between the clock signal and the data signal. In a first implementation, the digital filter provides a data retiming function by sending the output of the four bit counter to a digital delay element interposed between the data signal input and the input to the phase comparator. When the data is out of phase with respect to a local clock, the digital filter determines from a multitude of binary phase decisions the polarity of phase correction required, and feeds this back to the delay element. The delay element then adjusts the phase of the incoming data with respect to the phase of the local clock. In a second implementation of the present invention, the digital filter provides a phase lock loop function by sending the output of the four bit counter to a digital to analog converter (DAC). The DAC adjusts the output frequency of a voltage controlled oscillator (VCO). The output of the VCO is the data input to the phase comparator and the data signal is the clock input to the phase comparator. The VCO output is compared to the data signal in order to adjust the frequency and phase of the VCO and generate the proper clock signal from the incoming data.

Compact phase recovery scheme using digital circuits

A GaAs differential current switch (DCS) logic family is disclosed. Two cross-coupled, push-pull output buffer stages are coupled to the DCS logic circuit to increase the gain and to improve noise margins. The circuit is compatible with other GaAs logic families such as super buffer logic (SBL) or source follower logic (SFFL).

Two level differential current switch MESFET logic

Digital logic driving stage circuitry is provided connected between ground and a single voltage with an enhancement mode type field effect transistor and a depletion mode type field effect transistor connected source to drain in series between the single voltage and ground. The gate of the enhancement mode type field effect transistor is the input of the logic signal and the gate of the depletion mode type field effect transistor is connected to ground, with the output at the connection between the transistors. A family of digital logic circuits is provided with circuit units made up of an enhancement mode logic input, depletion mode load circuitry stage and an enhancement mode input grounded source follower load driving stage.

Two-stage digital logic circuits including an input switching stage and

In an analog-to-digital converter implemented in logic operating on the multiple lobes of a threshold curve, such as Josephson SQUIDs, two sampling registers are provided with sufficient offset to guarantee stability at sampling in one or the other regardless of other factors. Knowledge of bit value of the next lower bit order position permits determination of which sampling is valid. Encoder logic selects the valid sampling register retroactively. Each sampling register bit order position has two sampling SQUIDs and latching self-gated ANDs. Bias values are provided at higher orders to increment the phase offset so as to ensure low-to-high order readout. The lowest two bit orders may be implemented in simplified logic, effectively giving two bit order positions for logic and SQUIDs equal to that of one higher order bit position.

Look-back analog to digital converter

A transmission line having substantially reduced far-end forward wave crosstalk is characterized by a single layer of dielectric material having a thickness chosen to provide a forward wave coupling constant K.sub.F substantially equal to zero. The dielectric layer is located on a ground plane, and has a plurality of signal carrying conductors embedded in it. The thickness H of the dielectric underlayer below the signal carrying conductors is chosen to provide a transmission line having the selected values of impedance, etc. and substantially reduced forward wave crosstalk. The thickness t of the dielectric overlayer above the signal carrying conductors is chosen (for the selected value of thickness H of the dielectric underlayer) at the finite value critical thickness at which forward wave mutual capacitance and forward wave mutual inductance cancel to a null. The ground plane and the signal carrying conductors can be superconductors.

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Montrose, NY, United States of America

Carl J Anderson