Xilinx, Inc.

Carl H Carmichael

Chen Wei Tseng

Phil Edward Brinkley, Jr

Conrad A Theron

Donald H St Pierre, Jr

Gregory J Miller

Steven P Young

Austin H Lesea

Michael J Hart

Martin L Voogel

Jan Lodewijk De Jong

Kevin T Look

Shahin Toutounchi

Joseph J Fabula

Prasanna Sundararajan

Brandon Blodget

Cameron D Patterson

Edward S Peterson

Scott P McMillan

Edwin W Resler

Arun K Mandhania

Chakravarthy K Allamsetty

Trevor W Hardcastle

Thach-Kinh Le

A system includes a plurality of watchdog components. Each watchdog component is configured to receive a kick signal from its monitored function to determine whether the monitored function is active. Each watchdog component is further configured to receive a respective token from all watchdog components that the each watchdog component is connected to. The respective token determines whether its respective watchdog component has timed out. Each watchdog component is further configured to generate a token responsive to the kick signal and further responsive to the respective token from all watchdog component that the each watchdog component is connected to. Each watchdog component is further configured to transmit the generated token to the all watchdog components that the each watchdog component is connected to.

Distributed watchdog timer and active token exchange

A circuit for handling single event upsets includes a plurality of digital clock manager circuits. A plurality of counters are respectively coupled by their inputs to the outputs of the digital clock managers and a reset controller is coupled to the outputs of the counters. The reset controller is configured to determine an expected value of the counters. In response to an output value of one of the counters being less than the expected value, the reset controller triggers a reset of the digital clock manager coupled to the input of the one of the counters. In response to an output value of one of the counters being greater than or equal to the expected value, the reset controller continues operation without triggering a reset of a digital clock manager.

Single event upset mitigation

Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, a software portion of the design is compiled into software that is executable by a hard processor disposed on a single semiconductor chip with resources of an programmable logic device (PLD). A first synthesized version of a hardware portion of the design is generated for the PLD. A synthesized memory scrubber having an empty block for an address counter is generated, as well as a triple modular redundant (TMR) address counter. The memory in the first synthesized version of the hardware portion of the design is replaced with the memory scrubber, and a complete set of netlists is generated, including a TMR hardware portion of the design and a single instance of the synthesized memory scrubber. A configuration bitstream is generated from the complete set of netlists and stored for later use.

Implementing a user design in a programmable logic device with single event upset mitigation

A configuration management system is disclosed. For example, an embodiment of the present invention provides a configuration management system comprising a configuration storage device containing configuration data, and an integrated circuit, coupled to the configuration storage device, where the integrated circuit comprising at least one configuration management controller for managing a configuration of the integrated circuit in accordance with the configuration data, where the integrated circuit is deployed in a radiation tolerant device.

Method and apparatus for configuring an integrated circuit

SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. Correction techniques include reconfiguration of partial configuration data and 'scrubbing' based on anticipated SEUs.

Techniques for mitigating, detecting, and correcting single event upset effects

A configuration management system is disclosed. For example, an embodiment of the present invention provides a configuration management system comprising at least one configuration storage device containing configuration data, and a plurality of integrated circuits, coupled to said at least one configuration storage device, where the plurality of integrated circuits are coupled in a loop, where each of the plurality of integrated circuits comprising at least one configuration management controller for managing a configuration of another integrated circuit in the loop in accordance with the configuration data, where the plurality of integrated circuits is deployed in at least one radiation tolerant device.

A method of configuring an integrated circuit having programmable logic including the steps of generating a configuration bitstream in accordance with a configuration setup, storing the configuration bitstream into a portion of a memory, configuring the programmable logic of the integrated circuit with a first configuration portion of the configuration bitstream of the memory, monitoring the integrated circuit for at least one configuration error generated in response to an event upset, reconfiguring at least a portion of the programmable logic of the integrated circuit with a second configuration portion of the configuration bitstream in response to the at least one configuration error generated. The integrated circuit may operate normally during the process of reconfiguring the at least a portion of the programmable logic.

Method and apparatus for mitigating one or more event upsets

Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays

SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.

Single event upset in SRAM cells in FPGAs with high resistivity gate structures

Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the FPGA. According to the methods of the invention, the number of 'care bits' (bits associated with resources actually used in the design) is determined. The number of care bits as a proportion of the total number of configuration memory cells in the FPGA determines the 'SEU Probability Impact' (SEUPI) value. The &#x201c;Mean Time Between Upsets&#x201d; (MTBU) value is an estimate of how much time will elapse, on average, before one of the configuration memory cells in the FPGA is affected by an SEU. To obtain the &#x201c;Mean Time Between Failures&#x201d; for the design implemented in the FPGA, the MTBU value is divided by the SEUPI value.

Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA

SEU mitigation, detection, and correction techniques are disclosed. The mitigation techniques include: triple redundancy of a logic path is extended the length of the FPGA to avoid weak points susceptible to SEU effects; triple logic module and feedback redundancy provides redundant hardwired voter circuits at redundant logic outputs and voter circuits in feedback loops to ensure each logic module will receive accurate current state data even if it was upset by an SEU; enhanced triple device redundancy using three FPGAs is introduced, with a fourth device acting as a voting circuit and employing triple logic module and feedback redundancy of the second technique to provide nine instances of the user's logic and ensure complete accuracy in the system; critical redundant outputs are wire-ANDed together to ensure the output is asserted only when the redundant logic modules agree it should be asserted; redundant dual port RAMs are provided, with one port of each RAM dedicated to refreshing data and the remaining port of each RAM being available for use with the user's logic; and redundant clock delay locked loops (DLL) are provided and each DLL is monitored and reset if it does not remain in phase with the majority of the DLLs. The detection techniques include: configuration memory readback wherein a checksum for the expected value is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. The correction techniques include reconfiguration of partial configuration data and 'scrubbing' based on anticipated rather than actually detected SEUs.

Techniques for mitigating, detecting and correcting single event upset effects in systems using SRAM-based field programmable gate arrays

An FPGA interface device includes a microcontroller having a parallel port, a serial memory having an output port, and an on-board FPGA having a serial port coupled to the output port of the serial PROM and having a parallel port coupled to the parallel port of the microcontroller. The configuration design for the FPGA interface device's on-board FPGA and the firmware code for the interface device's microcontroller are stored in the serial memory. Upon power-up, the on-board FPGA reads the configuration design from the serial memory, and then configures itself accordingly. After properly configured, the on-board FPGA serially reads the microcontroller firmware code from the serial memory, parallelizes the firmware code, and thereafter enables the microcontroller to access the resulting parallel firmware code. Since both the on-board FPGA configuration design and the microcontroller firmware code are stored in a single memory, the dedicated parallel memory previously used to store the microcontroller firmware code may be eliminated, thereby advantageously conserving printed circuit board area.

Growing community of inventors

San Jose, CA, United States of America

Carl H Carmichael