Intel Corporation

Other

Philips Electronics North America Corporation

Intle Corporation

Andigilog, Inc.

Carl F Liepold

James T Doyle

John C Ciccone

Dc Sessions

Tim Beatty

Craig M Aykroyd

Jonathan Daniel McLin

A temperature sensor, in accordance with the principles of the invention comprises a silicon substrate. The silicon substrate includes a bandgap, an offset circuit for providing calibration offsets, and a gain block for providing an output that varies substantially linearly with changes in temperature of the substrate.

Temperature sensing circuit

A signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage. The timing recovery circuitry is configured to receive the differential output voltages from each of the differential comparators and is operative to derive a clock via edge detection and generate a recovered clock signal. The signal conversion circuitry is coupled with the timing recovery circuitry and the differential comparators and is operative to convert the differential output voltages into a binary equivalent. A method is also provided.

5-ary receiver utilizing common mode insensitive differential offset comparator

An adaptive temperature control circuit includes a first circuit for producing an error signal representing the difference between a preset temperature and an actual temperature and a second circuit coupled to the first circuit for producing a pulse width modulated output signal having a frequency greater than one hertz, wherein the width of the pulses is proportional to the error signal.

Adaptive temperature control circuit with PWM output

One embodiment of the present invention provides a flash analog-to-digital converter (ADC) based on a feedforward perceptron. The ADC includes a plurality of N stages to provide N digital signals. The plurality of N stages includes a first stage to provide a sum of an input current, related to a voltage to be converted, and of a reference current. The first stage provides a first digital signal in one of first and second states if the sum has one of first and second signs, respectively. The plurality of N stages further includes i stages, with i&equals;2 . . . N. Each stage i includes an output circuit and 2,sub-stages coupled to the output circuit. Each sub-stage includes an input and a hidden circuit coupled therebetween. The input circuit is configured to provide a first sum of the input current and of a first reference current. Each hidden circuit provides to the output circuit a second reference current when the first sum has a first sign. The output circuit generates an i,digital signal in one of a first and second states when a second sum of the input current and of the second reference current has one of first and second signs respectively.

Neural-flash analog-to-digital converter using weighted current similation

The present invention provides a differential amplifier. The differential amplifier includes first and second inputs and an output. The differential amplifier further includes a lateral bipolar transistor. The lateral bipolar transistor includes a well region that has a base region, an emitter region and first and second collector regions. The first and second collector regions are spaced apart from the emitter. The lateral bipolar transistor also includes a first gate, coupled to the first input, to overlay a space between the emitter region and the first collector region. Furthermore, the lateral bipolar transistor includes a second gate, coupled to the second input, to overlay a space between the emitter region and the second collector region. The differential amplifier further includes first and second load devices coupled to the first and second collector regions.

Differential amplifier with lateral bipolar transistor

The present invention provides a bi-directional low pass filtering method and apparatus for attenuating out-of-baseband components of data transmitted from an encoder to a decoder over a transmission medium. In one embodiment of the present invention, the bi-directional low pass filtering apparatus includes a Chebyshev filter that has a first phase response. This Chebyshev filter is coupled to a phase correction circuit, which has a second phase response. This second phase response of the phase correction circuit is designed to oppose the first phase response in order to offset variations in group delay in the data due to the Chebyshev filter.

Bi-directional low pass filtering method and apparatus

A programmable timing generator for creating a clock signal of variable duty cycle and frequency with a phase adjustment capability. To perform phase adjustment, the invention includes a mechanism which allows a frequency 'walking' or phase adjust to be inserted by just adding or subtracting one time constant into the high or low pulse at a certain time interval. In one embodiment, the invention uses two programable counters, with only one counter counting at a time. One counter counts the high phase of a generated output signal and the other counter counts the low phase of the output signal. The two counters, or a single multiplexed counter, allow the 'count high' value to be changed while the 'count low' value is being generated. The timing generator only creates outputs which change on rising clock edges of an input clock resulting in an output frequency which is directly related to the input clock. The input clock is divided by a value that can be either an integer or non integer value, with steps as small as 1/4. The output clock is therefore a certain number of integer clock periods high and a certain number of integer clock periods low.

Programmable frequency timing generator with phase adjust

A 'true' 16-bit second order Sigma-Delta based converter that has superior analog components and has a programmable comb filter which is coupled to the digital signal processor. This converter comprises a second order Sigma-Delta modulator and a programmable comb filter. The second order Sigma-Delta modulator dramatically attenuates the baseband quantization noise energy (which in turn increases the resolution of the converter), since its superior amplifiers and comparators enable it to oversample and coarsely quantize the analog input signal at a very high sampling frequency of 12 MHz. The amplifiers are class AB OTAs, which have cross coupled NMOS driven input stages, and cascoded output stages. Also, the common mode voltages are the optimal biasing points, and these voltages are kept constant by a differential input stage, by a PV independent temperature dependent current generator, by optimal device size, and by a common mode feedback circuitry. The programmable comb filter receives the coarsely digitized 1-bit output of the modulator at oversampling frequency F.sub.S, and provides a more accurate representation of the input signal to the DSP at slower sampling rate of F.sub.S /N. In addition, the comb filter uses a 20-bit data path, in order to enable the decimator (which is formed by the comb filter and by the FIR filter) to provide 16 bits of resolution to the DSP. The output of the programmable comb filter is then supplied to an FIR filter which is realized in the DSP, and this filter removes the remaining out-of-baseband noise.

Second order Sigma-Delta based analog to digital converter having

A subthreshold sense circuit for clamping an injected current at the input pins of an integrated circuit device before the injected current causes the voltage at the input pins to exceed the supply voltage by more than a diode's ON voltage. The subthreshold sense circuit is driven to operate in the linear region of the FETs. The subthreshold sense circuit of the present invention comprises level shifters, a subthreshold current source, a reference voltage generator, a subthreshold comparator, and a clamping circuit. The subthreshold current source generates a reference drain current to drive the sense circuit of the present invention in the linear region. A level shifter is connected to an input pin to shift the voltage level of the input pin by a subthreshold voltage level. The reference voltage generator provides a reference voltage to be compared with the subthreshold-shifted input voltage. The subthreshold comparator compares the subthreshold-shifted input voltage with the reference voltage level such that when the subthreshold-shifted input voltage from the input pin exceeds the reference voltage level, the subthreshold comparator will turn on. The clamping circuit is activated by the subthreshold comparator to clamp the input pin to less than one V.sub.D (ON) drop over the supply voltage by sinking the injected current at the input pin when the subthreshold comparator is turned on.

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Chandler, AZ, United States of America

Carl F Liepold