Nxp USA, Inc.

Motorola Corporation

Freescale Semiconductor,inc.

Carl Emil D'Acosta

Lakshminarayan Viswanathan

Jaynal Abedin Molla

David F Abdo

Justin Eugene Poarch

Paul Richard Hart

Mahesh K Shah

Lu Li

Geoffrey Tucker

John M Pigott

Randall C Gray

James Jen-Ho Wang

Fred T Brauchler

Norman Lee Owens

Darrel R Frear

Jerry Lynn White

Jerry D Cripe

Vivek Gupta

Craig L Jasper

Mali Mahalingam

Jerry S King

Dan A Banks

Microelectronic systems and components having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems and components. In various embodiments, the microelectronic system includes a substrate having a frontside, a socket cavity, and inner cavity sidewalls defining the socket cavity. A microelectronic component is seated on the frontside of the substrate such that a heat dissipation post, which projects from the microelectronic component, is received in the socket cavity and separated from the inner cavity sidewalls by a peripheral clearance. The microelectronic system further includes a bond layer contacting the inner cavity sidewalls, contacting an outer peripheral portion of the heat dissipation post, and at least partially filling the peripheral clearance.

Microelectronic components having integrated heat dissipation posts and systems including the same

Microelectronic systems having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the step or process of obtaining a microelectronic component from which a heat dissipation post projects. The microelectronic component is placed or seated on a substrate, such as a multilayer printed circuit board, having a socket cavity therein. The heat dissipation post is received in the socket cavity as the microelectronic component is seated on the substrate. Concurrent with or after seating the microelectronic component, the microelectronic component and the heat dissipation post are bonded to the substrate. In certain embodiments, the heat dissipation post may be dimensioned or sized such that, when the microelectronic component is seated on the substrate, the heat dissipation post occupies a volumetric majority of the socket cavity.

Microelectronic components having integrated heat dissipation posts, systems including the same, and methods for the fabrication thereof

Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.

Air cavity packages and methods for the production thereof

Embodiments of inductive communication devices include first and second galvanically isolated IC die and a dielectric structure. Each IC die has a coil proximate to a first surface of the IC die. The IC die are arranged so that the first surfaces of the IC die face each other, and the first coil and the second coil are aligned across a gap between the first and second IC die. The dielectric structure is positioned within the gap directly between the first and second coils, and a plurality of conductive structures are positioned in or on the dielectric structure and electrically coupled with the second IC die. The conductive structures include portions configured to function as bond pads, and the bond pads may be coupled to package leads using wirebonds. During operation, signals are conveyed between the IC die through inductive coupling between the coils.

Die-to-die inductive communication devices and methods

A stacked semiconductor device assembly () includes a device () having conductive traces () formed therein, and conductive interconnects () electrically connected to the conductive traces (). Another device () has conductive traces () formed therein and device pads () formed on an outer surface () of the device (). A method () entails attaching () a magnetic core () to an outer surface () of the device () and forming () the conductive interconnects () on the outer surface () using a stud bumping technique such that the interconnects () surround the magnetic core (). The conductive interconnects () are coupled () with the device pads () using thermocompression bonding to couple the device () with the device () to form a continuous device coil () wrapped around the magnetic core () from an alternating electrical connection of the traces (), the conductive interconnects (), and the traces ().

Stacked device assembly with integrated coil and method of forming same

A method of etching a semiconductor substrate (11) includes thinning (102) the semiconductor substrate (11), providing (103) a support layer (30) for the semiconductor substrate (11), providing (104) an etch mask (28) over the semiconductor substrate (11), and etching (105) the semiconductor substrate (11) using an etchant mixture of hydrofluoric acid, nitric acid, phosphoric acid, sulfuric acid, and a wetting agent at a temperature below ambient. The method is capable of using one etch step (105) and one etch mask (28) to form a plurality of trenches (12, 13) having the same width (15, 17) but different depths (16, 18) and different orientations. The method can be used to singulate different sizes and configurations of semiconductor dice from the semiconductor substrate (11).

Method of etching a semiconductor substrate

An ion implantation apparatus including a resolving aperture-shutter assembly (31) placed in the ion beam path (18). The resolving aperture-shutter assembly includes a movable shutter (34) and a shutter housing surrounding the movable shutter (34). Selected ions in an ion beam path (18) pass through a hole (44) in movable shutter (34) when the movable shutter (34) is in a first position, and are blocked by the solid surfaces when the movable shutter (34) is in a second position. The enclosure (32, 33, 39) completely surrounds the movable shutter (34). The enclosure (32, 33, 39) includes a first aperture (42) aligned with the ion beam path (18) for allowing the selected ions to enter the enclosure and a second aperture (41) aligned with the ion beam path (18) for allowing the selected ions to exit the enclosure after passing through the hole (44) in the movable shutter.

Ion implanter with beam resolving apparatus and method for implanting

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Mesa, AZ, United States of America

Carl Emil D'Acosta