Lsi Corporation

Lsi Logic Corporation

Carl Edward Gygi

Erik Paulsen

Mark Slutz

Andrew Hadley

Craig R Chafin

Luke Everett McKay

Brian J Varney

Brian K Einsweiler

Adam S Browen

Stuart L Nuffer

A system and method for improving message passing between a computer and peripheral devices is disclosed. The system and method for improving message passing between a computer and peripheral devices incorporate data checking on the command/message data and each scatter gather list element. The method in accordance with the present disclosure enables a peripheral device to check the integrity of the message and ownership of the scatter gather list element before the data is processed.

Scatter gather list for data integrity

A method for transparent debug of a hardware queue and recreation of an operational scenario comprising: use of a computer device to: monitor a plurality of inputs and outputs from a plurality of hardware queues associated as parts of a design; receive a request to save from an external source; pause one or more hardware queues upon command; receive hardware queue information from at least one of the paused hardware queues; dump said hardware queue information from at least one paused hardware queue; store the hardware queue information in a data storage connected to the computing device; compare the received information to stored data representative of a functional hardware queue; identify errors and failures in each monitored hardware queue from the comparing and; restore the hardware queue to a previous state.

Hardware queue for transparent debug

Methods and apparatus are provided for burst transfers of data between DDR memories and embedded processors during training of the PHY interface in an embedded system. An embedded system comprises an embedded processor having at least one cache controller; a memory, wherein the memory has an atomic memory access that comprises a plurality of clock edges; and a memory controller having a physical interface to convert digital signals between the embedded processor and the memory, wherein the cache controller executes a training process to determine a delay through the physical interface for each of the plurality of clock edges using a burst transfer of data. The burst transfer comprises reading a data pattern from the memory and storing the data pattern in one or more registers in the embedded processor.

Methods and apparatus for burst data transfers between double data rate (DDR) memories and embedded processors during training

Apparatus and methods for improved high-speed communication by exchanging low-speed information regarding the high-speed exchanges over the same communication medium. In one exemplary embodiment, a communication device includes a high-speed transceiver adapted to exchange high-speed data with another device via a communication medium using high-frequency signals. The device also includes a low-speed component adapted to exchange low-speed information over the same communication medium as low-frequency signals. The low-frequency signals may be applied as common mode signals to a differential communication path so as to not interfere with the high-speed data exchanges. In another embodiment, a high-pass filter may be included in the device to remove the low-frequency signals before the high-speed data is applied to the high-speed transceiver. Responsive to receipt of the low-speed information, a device may adjust parameters of the transceiver to improve the high-speed data exchanges.

Apparatus and methods for improved high-speed communication systems

A method and system for performing diagnostics and validation operations on a device under test uses near natural language commands. A host machine controls the testing either locally or remotely, such as through the Internet. Various options for running a test or battery of tests on the device under test include entering commands through a prompt line on a graphical user interface, reading commands from a file, or manipulating graphical objects representing components or devices and operations on a graphical user interface. A script may serve as a metric to determine the successfulness of a test or battery of tests of the device under test.

Method, system and programming language for device diagnostics and validation

Methods and structure for standardized communication between a test operator, a host system, and an embedded system under test. Test program instructions are designed, written for, and executed on, an embedded system under test in accordance with standard API functions for message exchange. Still further, the invention provides for standards in the user interface to select a desired test, to start the test with defined parameters and to present reply and status information to the test operator. These user interactions are defined in a test configuration language of the present invention and preferably incorporated with the executable image file to define an integral test vehicle file. The present invention thereby reduces test sequence development time by providing standard API functions for message exchange between a host system test application and the system under test and provides for standardized user interaction in a flexible, easily maintained design language.

Methods and structure for improved testing of embedded systems

The present invention is a method and system for providing a complete validation of an initiator and target within bus architecture. A target's behavior may be controlled by an initiator. Control of the target may be through execution of initiator commands including vendor unique commands relating to desired characteristics for testing. The initiator's response to the target's behavior may be verified due to the handshaking communication protocol between a target and initiator. Additionally, by altering the behavior of the target to test initiator response, a target's behavior is also validated.

Method and apparatus for controlling SAS/fibre target behavior from a host

A method for data verification in a data storage environment including the steps of (A) sending a command from an initiator to a target, where the command defines an expected data pattern, (B) sending a block write command from the initiator to the target, where the write command initiates sending data from the initiator to the target, (C) comparing data received to the expected data pattern and (D) generating a status indication in response to the comparison.

Method and/or apparatus for SCSI target verification

A communications layer is provided between a host-based SCSI initiator and a SCSI target device to fully automate the validation process. The communications layer allows the host to direct variation and modification of the target parameters and behavior using vendor unique commands. The behavioral modification aims to establish interoperability by conforming the behavior of the target to the host behavior. The host-based initiator transports a suitable command structure to the target device containing appropriate ones of the vendor unique commands and associated parameter data. The target executes and otherwise processes the command structure to effectuate a reconfiguration according to the specifics of the command code. The command code is sufficient to fully reconfigure the SCSI target. Accordingly, the reconfiguration process is carried out in a fully automated fashion.

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Colorado Springs, CO, United States of America

Carl Edward Gygi