Motorola Corporation

Ford Motor Company Limited

Carl D Wiseman

Jules D Campbell, Jr

Rollie Morris Fisher

Rudolf Bettelheim

Mark R Heene

William D Huston

Colleen M Collins

Naji Chafic Naufel

John R Scollard

Louis Rodriguez, Jr

Tushar Patel

Yah Bin Sim

Sang Quan

Clare C Leiby, Iii

Yong Hyon Kim

Serial communication circuitry (10) having multiple queues (11-14) for use in a data processing system (95). Each queue (11-14) has multiple entries (52). Serial transfers from the multiple queues (11-14) are carried out under the control of global parameters (e.g. 205, 209), per-queue parameters (e.g. 211-212, 214-217), and per-entry parameters (e.g. 350-361). Each queue can be programmed to have a different set of per-queue parameters, and each entry within a queue can be programmed to have a different set of per-entry parameters. In addition, serial communication circuitry (10) can perform serial data transfers in response to the assertion of a trigger signal (30) from a source such as a timer (63) or a central processing unit (61). As a result, data transfers can be more precisely related to a particular timing signal or set of timing signals.

Queued serial peripheral interface having multiple queues for use in a

An electronic circuit (100) for reducing electromagnetic interference includes a plurality of circuit elements (130, 140, 150) to which a set of bussed logic signals (343) generated by a set of first circuits (342) is distributed by a logic clock (120). The electronic circuit (100) further includes a plurality of cascaded busses (355, 135, 335) including a last cascaded bus (335) having a last enablement phase. Each of the plurality of cascaded busses (355, 135, 335) couples a set of amplified logic signals (355, 135, 335) from one of the plurality of circuit elements (358, 359, 336) to another one of the plurality of circuit elements (359, 336, 322). The set of amplified logic signals (355, 135, 335) of each of the plurality of cascaded busses is enabled during an enable period (351, 352, 330) which lasts beyond an end of the last enablement phase.

Electronic circuit having phased logic busses for reducing

An analog-to-digital conversion module, QADC (1), and method minimize software involvement by providing a pause capacility. Each queue in the QADC (1) has one or more Conversion Command Words, CCWs (82), in a Conversion Command Word Table (62). Each conversion command word, CCW (82), has a Pause bit which can be used to create multiple sub-queues of A/D conversions without requiring the use of interrupts. The Pause bit can be used to place a queue in a pause state. When a queue enters a pause state, the scanning of CCWs (82) is stopped. The queue must then receive a trigger in order for the scanning of CCWs (82) to continue again.

Automatic A/D converter operation with pause capability

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Austin, TX, United States of America

Carl D Wiseman