International Business Machines Corporation

Carl D Dietz

Kathryn Jean Hoover

Christopher Hans Olson

Robert Thaddeus Golla

A processing system and method of operation are provided. First translation information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first translation information and a first portion of a first address. Second translation information is stored. A logic state of a second match line is selectively modified in response to a comparison between the second translation information and a second portion of the first address. The logic state of the second match line is selectively modified in response to the logic state of the first match line. A second address is selectively output in response to the logic state of the second match line.

Translation lookaside buffer for faster processing in response to

A method and system within a processor are disclosed for executing selected instructions among a number of instructions stored within a memory, wherein the processor has a maximum of instructions that can dispatched for execution during each processor cycle. A subset of the instructions are fetched from the memory for execution. A determination is then made whether the set of instructions includes an unresolved branch instruction. In response to a determination that the set of instructions includes an unresolved branch instruction, a prediction is made whether a branch indicated by the branch instruction will be taken or will not be taken. In response to a prediction that the branch will be taken, a nonsequential target instruction indicated by the branch instruction is fetched from memory. A determination is made whether the maximum number of instructions can be dispatched for execution during a processor cycle subsequent to the branch prediction without dispatching instructions within the sequential execution path. In response to a determination that less than the maximum number of target instructions can be dispatched in the processor cycle subsequent to the branch prediction without dispatching instructions within the sequential execution path, an instruction within the sequential execution path is speculatively dispatched for execution. In response to refutation of the branch prediction, the fetch of the nonsequential target instruction is cancelled and the instruction within the sequential execution path is executed, thereby minimizing a performance penalty incurred by the processor due to the mispredicted branch.

Method and system for minimizing branch misprediction penalties within a

Content addressable memory circuitry and a method of operation are provided. First information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first information and second information. Also, third information is stored. A logic state of a second match line is selectively modified in response to a comparison between the third information and fourth information. A logic state of the second match line is selectively modified in response to the logic state of the first match line.

Content addressable memory circuitry and method of operation

Comparator circuitry and a method of operation are provided. First and second match lines are precharged. First and second information are compared, and the first match line is selectively discharged in response thereto. Third and fourth information are compared, and the second match line is selectively discharged in response thereto. The second match line is discharged in response to discharging the first match line.

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Kyle, TX, United States of America

Carl D Dietz