Hewlett-Packard Development Company, L.p.

Hewlett-Packard Company

Institute for the Development of Emerging Architectures, L.l.c.

Carl D Burch

William B Buzbee

Rajiv Kumar

The present invention, in various embodiments, provides techniques for retiring instructions that typically complete early as compared to most instructions. In a first embodiment, at each stage of the various processing stages, each instruction capable of early retirement is processed in accordance with that stage. At a particular stage, if the instruction meets the criteria for early retirement, then the instruction is terminated, e.g., 'retired,' and the system is updated to reflect that the instruction has been terminated. However, if, at that particular stage, the instruction does not meet the criteria for early retirement, then the instruction is processed to the next stage, and it is determined again whether the instruction meets the criteria for early retirement. If the instruction meets the criteria, then the instruction is terminated, or if the instruction does not meet the criteria, then the instruction is processed to the next stage, and so on, until the instruction is retired. In a second embodiment, it is predetermined that early-completion instructions are to be retired at a particular stage. Consequently, all instructions are processed normally and early-completion instructions are retired when they reach that particular stage. For example, early-completion instructions are retired out-of-order after they reach a particular stage in an instruction queue, even though they meet the early-retirement criteria prior to entering the queue. In a third embodiment, early-completion instructions are retired out-of-order when an instruction queue is full. As a result, all instructions are processed normally until the instruction queue is full. At that time, the system is frozen, e.g., all units stop processing instructions. For each instruction in the instruction queue, if the instruction meets the criteria for early retirement, then the instruction is terminated and the system is updated to reflect that the instruction has been terminated. The system is then unfrozen, and all units resume their functions.

Retiring early-completion instructions to improve computer operation throughput

The present invention provides a system and method for optimizing compilation time of a program. In architecture, the system includes a compiler that generates the least one block of code from the program; and a compilation optimizer. The compilation optimizer generates a hash value for a block of code in the program and stores the hash value with the block of code if the hash value is not equal to a prior hash value for the block of code; and skips the optimization of the block of code if the hash value equals the prior hash value. The present invention can also be viewed as a method for optimizing compilation time of a program. The method operates by generating a current hash value for a block of code in the program, skipping the optimization of the block of code if the current hash value equals a prior hash value, and storing the current hash value with the block of code if the hash value is not equal to the prior hash value for the block of code.

Method and system for optimizing compilation time of a program by selectively reusing object code

The present invention provides techniques for retiring instructions that typically complete early as compared to most instructions. In an embodiment, instructions capable of early retirement are processed in accordance with the various processing stages. At a particular stage, if an instruction meets the criteria for early retirement, then that instruction is terminated, e.g., 'retired,' and the system is updated to reflect that the instruction has been terminated. However, if the instruction does not meet the criteria for early retirement, then the instruction is processed to the next stage, and it is determined again whether the instruction meets the criteria for early retirement. If the instruction meets the criteria, then the instruction is terminated, or if the instruction does not meet the criteria, then the instruction is processed to the next stage, and so on, until the instruction is retired.

Techniques are provided for retiring instructions that typically complete early as compared to most instructions. In an embodiment, all instructions are processed normally until the instruction queue is full. At that time, the system is frozen, e.g., all units stop processing instructions. For each instruction in the instruction queue, if the instruction meets the criteria for early retirement, then the instruction is terminated and the system is updated to reflect that the instruction has been terminated. The system is then unfrozen, and all units resume their functions.

Retiring instructions that meet the early-retirement criteria to improve computer operation throughput

Dynamic translation is used during debugging of a computer application process. The computer application process resides in a computing system in which blocks of code within a shared library are utilized by the computer application process. The blocks of code within the shared library are also available to be utilized by other applications in the system. During runtime, the computer application process is dynamically translated to produce translated code. The dynamic translation includes translation of a first block of code within the shared library to produce a translated block of code. The translated block of code is included within the translated code. Debugging code, such as a break instruction, may then be added to the translated code. Alternatively, only blocks of code within the shared library which are called by the computer application process or modified by a debugger are dynamically translated. In this alternative case, the object code for the computer application process is executed without being dynamically translated.

Use of dynamic translation to provide breakpoints in non-writeable object code

An incremental selective compiler tool that minimizes compilation of intermediate code files by reusing object code files during the compilation and linking process. The compiler tool determines when the results of previous compilations of intermediate code files, that is object code files, may be reused in subsequent execution. That is, the incremental selective compiler tool determines whether compiler directives of an intermediate code file have changed between invocations of the linker, thereby requiring recompilation of the intermediate file to complete the linking process. The present invention also incrementally recompiles only those intermediate code files with compiler directives that have changed since the prior code generation. The incremental selective compiler tool supports arbitrary copying and movement of intermediate code files and object code files within a file system and between file systems while continuing to enable reuse of the object code files.

Method and apparatus for incremental selective compilation of intermediate code files during computer system compilation and linking

A method of operating a digital computer to provide instrumentation data for a shared library running in an environment in which programs are loaded and unloaded by a loader. The environment supports the operation of at least one program in addition to the shared library, the program utilizing at least one function provided by the shared library. The operating environment includes storage for a predetermined environment variable that may be read by any program running in the environment. The method includes the steps of causing the loader to examine the environment to determine if the predetermined environment variable has been set; and storing profile based optimization data stored in the shared library code in a location specified by the predetermined environmental variable if the predetermined environmental variable was present in response to a command being sent to the loader. The profile based optimization data is normally stored when the shared library is unloaded from the operating environment by the loader.

Profile based optimization of shared libraries

An enhanced unwind facility is more extensible, much faster, and uses smaller tables than presently known schemes. In broad terms, the unwind facility trades bytes that are used for addresses and region lengths in known schemes for a stream of bit fields parallel to the instruction stream. This arrangement allows an unwind library to compute a current regions' attributes by indexing instead of by a binary search. This arrangement also leads to an extensible design that does not require significant effort on an occurrence-by-occurrence basis in both the linker and the unwind library when additional services are required, e.g. register use areas for the debugging of optimized code.

Enhanced stack unwind facility

The inventive software device simulates the cycles of a digital device on a computer system. The inventive simulator allows model bits to be computed in parallel and provides improved time-to-solution performance. The simulator uses words and bit-wise operations of the computer as vector processors. The simulator creates abstract representations having inputs and outputs for each component within the digital device. The simulator sorts the abstract representations to form groups of identical representations. Then, the simulator sequentially assigns each output of each representation in the group to one or more output words for that group. The concatenation of the output words for all groups is the output vector for the simulation. Next, the simulator maps each output bit to one or more offsets in an input vector for the simulation. Then, the simulator generates CPU instructions for each group that perform the bit calculations done by the represented component. The CPU instructions operate on the bits in the input vector to produce output bits stored in the output vector loop for each representation in the group. Finally, the simulator copies the bits from the output vector to the bits' mapped locations in the input vector to ready the next simulation cycle. This transforms the simulator into a loop-oriented application and reduces the code size of the model.

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Cupertino, CA, United States of America

Carl D Burch