Intel Corporation

Carl C Scafidi

Tse-Yu Yeh

Gary N Hammond

Mircea Poplingher

John H Crawford

Ashish V Choubal

Michael Paul Corwin

Wenliang Chen

Bryan D Boatright

Mitchell Alexander Poplingher

Monis Rahman

Ben J Eapen

C Glenn Shirley

Embodiments include a system for minimizing storage space required for tracking load instructions through a pipeline in a processor. Store instructions are tracked in a separate queue and only load instructions that require speculation on data or addresses are tracked in a load table and flagged in the reorder buffer. This system improves system performance by reducing energy and space requirements.

Utilizing an advanced load address table for memory disambiguation in an out of order processor

A method and apparatus for providing a source operand for an instruction to be executed in a processor. Some embodiments may include a register file unit that has registers and a scheduler to schedule instructions. In some embodiments, the scheduler is to asynchronously receive an instruction and a source operand for that instruction, the source operand being received from the register file unit.

Method and apparatus to provide a source operand for an instruction in a processor

In accordance with various embodiments of the present invention, a cache-equipped semi-conductor device is provided with enhanced error detection logic to detect a first location-independent error within an area of the cache memory and prevent further use of the area if the error is determined to be the second consecutive error associated with a common area.

Methods and apparatuses for reducing infant mortality in semiconductor devices utilizing static random access memory (SRAM)

A pipelined microprocessor having a branch prediction unit implemented in an instruction pointer generation stage of the microprocessor. The branch prediction unit includes a memory device having at least a first entry configured to hold at least a part of a memory address of a pre-selected branch instruction and at least a part of a memory address of a branch target corresponding to the pre-selected branch instruction. The branch prediction unit compares an instruction pointer of an instruction to be executed with the memory address of the pre-selected branch instruction. In response to a match between the instruction pointer and the memory address of pre-selected branch instruction, the unit causes the microprocessor to fetch an instruction corresponding to the branch target. In one embodiment, the instruction pointer generation stage of the microprocessor is implemented as a first stage of the pipelined microprocessor. In addition, the branch prediction unit is compares the instruction pointer and the memory address of the pre-selected branch instruction during a single clock cycle in which the instruction pointer is generated.

Method and apparatus for performing early branch prediction in a microprocessor

A processor architecture with an instruction set having a predict instruction, the predict instruction providing static prediction information and a statically predicted target address to the processor for a branch instruction. The processor decodes a predict instruction to obtain an associated pair of addresses comprising a predicted target address and a referenced instruction address, and fetches a predicted target instruction having an instruction address matching the predicted target address when a fetched and decoded branch instruction has an instruction address matching the referenced instruction address.

Processor and instruction set with predict instructions

A method and apparatus for generating respective branch predictions for first and second branch instructions, both indexed by a first instruction pointer, is disclosed. The apparatus includes dynamic branch prediction circuitry for generating a branch prediction based on the outcome of previous branch resolution activity, as well as static branch prediction circuitry configured to generate a branch prediction based on static branch prediction information. Prediction output circuitry, coupled to the both the dynamic and static branch prediction circuitry, outputs the respective branch predictions for the first and second branch instructions in first and second clock cycles to an instruction buffer (or 'rotator'). Specifically, the prediction output control circuitry outputs the branch prediction for the second branch instruction in the second clock cycle and in response to the initiation of a recycle stall during the first clock cycle. The receipt of the predictions and their corresponding branch instructions at the instruction buffer is thus synchronized, and the opportunity of generating a prediction for the second branch instruction is not lost.

Growing community of inventors

Fort Collins, CO, United States of America

Carl C Scafidi