Motorola Corporation

Carl C Hanke

Carlos D Obregon

Ahmad H Atriss

William H Gulliver

Timothy W Sutton

A phase lock loop (PLL) reduces output phase jitter by averaging an input clock signal and a delayed input clock signal. A control signal selects between the input clock signal and the delayed input clock signal for providing a reference clock signal for the phase lock loop. The output oscillator signal of the PLL is divided by a predetermined integer value for providing the control signal to select between the input clock signal and the delayed input clock signal. The PLL establishes phase lock to the input clock signal during a first state of the control signal. The PLL next establishes phase lock to the delayed input clock signal during a second state of the control signal such that the average value of the output clock signal of the PLL is substantially constant.

Circuit and method of reducing phase jitter in a phase lock loop

A PLL lock indicator circuit for indicating when a phase-lock-loop circuit is in lock includes a gate circuit coupled to the phase/frequency detector of the phase-lock-loop circuit for providing an output logic signal that is responsive to output logic signals from the phase/frequency detector being in a predetermined state. A counter circuit is enabled by the output logic signal of the gate circuit for providing an output logic signal when the counter circuit has reached a predetermined count. A latch circuit is responsive to the output logic signal of the counter circuit for providing a lock signal at an output terminal of the circuit, the lock signal being indicative of when the PLL circuit is in phase lock.

Phase-lock-loop lock indicator circuit

The output signal of a CMOS power-on reset circuit changes state upon detecting a predetermined threshold of the power supply voltage during the start-up transient. During the power-up of the power supply voltage, the output signal of the power-on reset circuit ramps up with the power supply voltage until the latter reaches a first predetermined level whereat a control signal begins to track the increasing power supply voltage, less two diodes potentials. Upon reaching the turn-on potential of a transistor, the control signal activates an inverter to substantially reduce the output signal signifying that the power supply voltage level is sufficient for the operation of external circuitry. The output signal then disables the current flowing through the power-on reset circuit to save power consumption.

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Mesa, AZ, United States of America

Carl C Hanke