International Business Machines Corporation

Carl B Ford, Iii

Pak-kin Mak

Michael Andrew Blake

Kevin W Kark

Liyong Wang

Bruce G Hazelzet

Gary E Strait

Roger A Rippens

Gary A VanHuben

Donald J Swietek

Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-detect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.

Relocatable storage protect keys for system main memory

A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board. Each DIMM has memory regions comprising one of a plurality of physical entities hereafter referred to as memory macros which are relocatable regions which contain SP Keys and data set storage in the DIMM physical memory. These memory macros SP Key regions define an arbitrary logic structure for main storage which has a hard physical boundary.

Processor memory array having memory macros for relocatable store protect keys

A modular multiprocessor computer system having a plurality of nodes each being in communication with each other via communication links. The plurality of nodes each have local memory and local cache accessible by the other nodes. The plurality of nodes each also having a cache directory, one or more processing units, and a memory coherent directory to keep track of the scope of ownership of data within the modular multiprocessing computer system. The local memory and the local cache contain configurable regions of storage, wherein memory coherency traffic on the communication links between the nodes is controlled through the use of the memory coherent directory during a data request.

Memory management for a symmetric multiprocessor computer system

A system for monitoring hardware events in a computer system implements a hardware event monitor of control registers and has programmable generic fields which can be internally or externally programmed for monitoring events ranging from simple operations to complex event sequences. Using programmed criteria incorporated into the hardware event monitor to events within said computer system are monitored by initiating successive compares of programmed criteria with processing events. The hardware event monitor can trigger external actions upon successful detection of compares indicating that all criteria programmed into the hardware event monitor have been achieved. None of the bits within the Control Registers are mutually exclusive which allows multiple scenarios to be programmed. The hardware event monitor and system trace controls act as a single unified entity with remote programming of said hardware event monitor and trace controls over a UBUS to permit capturing and logging problem debugging and instrumentation data for use in remote system administration, technical support assistance, field and customer engineering applications, and performance analysis, and hardware error injection for recovery and diagnostic testing, and enabling dither to break resource deadlocks.

Programmable hardware event monitoring method

A hierarchical cache architecture that reduces traffic on a main memory bus while overcoming the disadvantages of prior systems. The architecture includes a plurality of level one caches that are of the store through type, each level one cache is associated with a processor and may be incorporated into the processor. Subsets (or 'clusters') of processors, along with their associated level one caches, are formed and a level two cache is provided for each cluster. Each processor-level one cache pair within a cluster is coupled to the cluster's level two cache through a dedicated bus. By configuring the processors and caches in this manner, not only is the speed advantage normally associated with the use of cache memory realized, but the number of memory bus accesses is reduced without the disadvantages associated with the use of store in type caches at level one and without the disadvantages associated with the use of a shared cache bus.

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Poughkeepsie, NY, United States of America

Carl B Ford, Iii