Lsi Corporation

Lsi Logic Corporation

Carl Anthony Monzel, Iii

Ramnath Venkatraman

Subramanian Ramesh

Michael Norris Dillon

Gary Scott Delp

Scott Allen Peterson

David A Gardner

Robert C Armstrong

Bret Alan Oeltjen

A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

Basic cell architecture for structured ASICs

An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.

Integrated circuit cell architecture configurable for memory or logic elements

A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

Basic cell architecture for structured application-specific integrated circuits

A re-configurable core cell is provided that can be used as either a content addressable memory cell or a dual-ported static read only memory cell. The re-configurable core cells are pre-diffused on the chip. The core cells may then be configured as CAM or SRAM with a metal layer. The peripheral logic of the CAM or SRAM may be built from gate array devices.

Re-configurable content addressable/dual port memory

A pre-diffused high density array of core memory cells is provided in a metal programmable device. The peripheral logic is made up of gate array cells in the metal programmable device. The peripheral logic may be configured to access the core memory cells as various memory types, widths, depths, and other configurations. If the entire memory is not needed, then the unused memory cells can be used as logic gates. The application-specific circuit, including peripheral logic, memory interface logic, and memory configuration is programmed with a metal layer.

Growing community of inventors

Lakeville, MN, United States of America

Carl Anthony Monzel, Iii