International Business Machines Corporation

Carl Alfred Bender

Peter Kenneth Szwed

Jeffrey M Turner

Howard M Haynie

Nihad Hadzic

Kevin J Gildea

Richard A Swetz

Peter H Hochschild

Rama Krishna Govindaraju

Douglas James Joseph

Jeffrey C Hanscom

Nicholas P Rash

Douglas G Balazich

Chulho Kim

Jay Robert Herring

Derrick LeRoy Garmire

Gautam H Shah

Raymond Wong

Paul D DiNicola

Jamshed H Mirza

Steven Mark Thurber

Adalberto Guillermo Yanes

Patrick Allen Buckland

Ashutosh Misra

Michael J Cadigan, Jr

Thomas D Needham

Fu Chung Chang

Kathy Sue Barkey

Harold Edgar Roman

Daniel Gerard Smyth

John R Flanagan

Daniel Francis Casper

Robert Francis Bartfai

Gerard M Salem

Clinton E Bubb

Donald G Grice

Aruna V Ramanan

Kevin J Reilly

Christine M Desnoyers

Michael Patrick Muhlada

An Ding Chen

Ben Jesse Nathanson

Karen F Rash, Legal Representative

Donna C Myers

William R Milani

Jaroslaw Nieplocha

Antoinette E Vallone

Vadim M Tsinker

Sheryl M Genco

Singpui Zee

Michael J Cardigan, Jr

Rama J Govindaraju

Richard Swetz

Peter Heiner Hochschild

A method, computer program product, and system maintain virtual product data (VPD) in a computer system. The method includes a processor obtaining a first indicator, which may indicate a repair has commenced in a computer system or an initial program load has commenced in the computer system, accessing VPD related to the computer system, and duplicating the VPD to create a copy of the VPD. The processor stores the copy of the VPD in at least one computing element internal to the processor or accessible to the processor via a communications network. The processor obtains a second indicator that indicates that the initial program load is complete or that the repair process is complete, compares the VPD to the copy of the VPD, and determines whether to replace at least a portion of the VPD with at least a portion of the copy of the VPD.

Preserving virtual product data in a computer system

A calculation, prediction and validation method can include receiving a portion of a data packet in a data buffer, computing, in a processor, information related to the checksum of the data packet based on the portion of the data packet and processing the data packet in the processor.

Checksum calculation, prediction and validation

There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated 'pre-counter' while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the 'sweeper' state machine accesses the pre-counter.

RAM based implementation for scalable, reliable high speed event counters

A computer program product is provided for performing input/output (I/O) processing. The computer program product is configured to perform: generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data discard field; generating an address control structure specifying a local channel memory location of a corresponding ACW; receiving one or more data transfer requests from a network interface that each corresponding address control structure information; accessing an ACW and routing the data transfer request to a host memory location specified in the ACW; and responsive to encountering an error during at least one of the accessing and the routing, discarding the one or more data transfer requests and setting the data discard field to a value configured to instruct a channel to discard any subsequent data transfer requests associated with the ACW.

Fibre channel input/output data routing including discarding of data transfer requests in response to error detection

Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.

Re-programming programmable hardware devices without system downtime

A checksum calculation, prediction and validation system includes a host system, a network interface, a reception pipeline disposed between the host system and network interface and configured to calculate an expected full checksum related to packets received in the host system and a transmission pipeline disposed between the host system and network interface and configured calculate factors related to packets for transmission on the network interface.

A mechanism for temporarily stalling selected Direct Memory Access (DMA) operations in a physical input/output (I/O) adapter in order to permit migration of data between physical pages that are subject to access by the physical I/O adapter. When a request for a DMA to a physical page in system memory is received from an I/O adapter, a migration in progress (MIP) bit in a translation control entry (TCE) pointing to the physical page is examined, wherein the MIP bit indicates whether migration of the physical page referenced in the TCE to another location in system memory is currently in progress. If the MIP bit indicates a migration of the physical page is in progress, the DMA from the I/O adapter is temporarily stalled while other DMA operations from other I/O adapters to other physical pages in system memory are allowed to continue.

Stalling of DMA operations in order to do memory migration using a migration in progress bit in the translation control entry mechanism

Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

Avoiding non-posted request deadlocks in devices by holding the sending of requests

A task obtained by a communications processor is decomposed into one or more requests that form a request group. The requests of the request group are sent to main memory and responses to those requests are expected. There may be requests for a plurality of request groups being processed concurrently. However, responses to the request groups are to be returned to the communications processor in the order in which the request groups were sent from the communications processor. To ensure this ordering, dependencies between the request groups are tracked by hardware coupled to the communications processor.

Use of hardware to manage dependencies between groups of network data packets

In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.

Efficient probabilistic duplicate packet detector in computer networks

In a communications network having a plurality of nodes adapted to communicate with each other, and more than one path available between most source-destination node-pairs, a network interface is associated with each node. Each network interface has a plurality of route tables for defining a plurality of routes for transferring each packet from a source node to a destination node. Each network interface further includes a path status table of path status indicators, e.g., bits, for indicating whether each route in the route tables is usable or is unusable as being associated with a fault. The network manager monitors the network to identify faults and provides the path status indicators to the respective network interfaces. Failed routes in the network are avoided based on the path status indicators. When a failed route is restored, such that the route is usable again, the path status table indicates that the usable state is restored. A balance of route usage in the network is maintained, without modifying routes or establishing different routes, enabling reliable and high-performance message transfer.

Reliable message transfer over an unreliable network

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Highland, NY, United States of America

Carl Alfred Bender