Teranex, Inc.

Teranex Systems, Inc.

Carl Alan Morris

Kevin Dennis

Woodrow L Meeker

Clara Ka Wah Sung

Howard Del Fava

System and method for reading and writing pixel aligned subframes from a frame buffer in a parallel processing system are disclosed. Optimal bandwidth access of the frame buffer requires that data be moved in bursts having multiple data words. Subframes are specified at X and Y locations within the image frame with a resolution of one pixel. In addition, subframes within a row may overlap each other and consecutive subframe rows may also overlap. Memory control logic of the invention provides pixel packing and unpacking and storing selected pixel data in a cache memory. Reading and writing to the frame buffer is provided in a manner that makes optimal use of the frame buffer internal architecture. Other capabilities of the memory control logic include decimation of pixel data during input, suppression of redundant frame buffer writes, and accessing image frame data in an interlaced manner.

Method and apparatus for reading and writing pixel-aligned subframes in a frame buffer

Selectively distributing a plurality of data items to a plurality of hardware destinations that share a common bus involves, for each one of the data items, determining which of the hardware destinations the data item should be distributed to, wherein at least one of the data items should be distributed to two or more hardware destinations. The data item is then supplied to the common bus and, for each of the hardware destinations to which the data item should be distributed, a corresponding hardware destination signal is generated that causes the data item to be received in the hardware destination from the common bus, wherein for each data item, the corresponding hardware destination signals are generated substantially simultaneously. This may be applied in a number of scenarios, including the distribution of data items to a plurality of processor boards, and to the distribution of data items to a plurality of channels within a single processor board. A similar approach is provided for forming a sequence of data items by selectively collecting a plurality of data items from a plurality of processor boards in a multiprocessor system.

Distribution, processing, and reconstruction of variable-sized images using multiple processor arrays

A memory-like I/O system is provided for interfacing a processing element array with a host system. The I/O system includes cornerturn logic for converting data written to the processing element array from horizontal format to vertical format and for converting data read from the processing element array from vertical format to horizontal format. Addressable interface memory is provided and includes a first bank for receiving and storing data which has been output from the cornerturn logic and for outputting that data for delivery to the processing element array. The addressable interface memory includes a second bank for receiving and storing data which has been output from the processing element array and for outputting that data for delivery to the cornerturn logic. The interface of the invention can provide support for concurrent I/O and processing, thereby allowing processing and I/O operations to proceed in parallel. The memory used to implement the interface can be used for on-chip paging to significantly reduce or eliminate the need for the slower and more costly off-chip paging.

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Orlando, FL, United States of America

Carl Alan Morris