International Business Machines Corporation

Carl A Malmquist

John David Wilson

Richard Allen Kelley

Douglas R Chisholm

Donall G Bourke

Hartmut R Schwermer

Charles B Perkins, Jr

Roy Y Liu

Gregory D Float

Richard L Place

John M Nelson

In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous 'handshaking' manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

Coupled synchronous-asychronous bus structure for transferring data

Method for performing inter-unit data transfer operations among a

In a data processing system, an input output bus unit (IOBU) is connected one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous handshaking manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, message acceptance operation.

Method for transferring information between main store and input output

Input output interface controller connecting a synchronous bus to an

An arbitration apparatus for use within a computer system comprises a plurality of individual arbiters arranged in a particular configuration wherein some individual arbiters are higher in the particular configuration than a specific arbiter and some individual arbiters are lower in the particular configuration than the specific arbiter. Each arbiter has a request terminal for receiving access request signals, requesting access to a shared system bus, and an enable terminal for receiving an enabling signal. The enabling signal is generated and energizes the enable terminal of the specific arbiter if access requests are not received by higher arbiters in the particular configuration relative to the specific arbiter. If an access request signal energizes an arbiter and an enabling signal energizes the arbiter, an access grant signal is developed from the arbiter. If more than one access request signal energizes the arbiter at the same time, a command rotor, connected to the arbiter, determines the priority of access of the request signals to the shared bus in response to the 'rotation' of the command rotor. If the access request signal is of a predetermined type, a pre-emptive grant signal may be developed from its arbiter even in the absence of an access request if there are no higher requests and no lower grants. If a refresh request is received by an arbiter when its enabling signal is not received, the refresh request is latched, and a refresh takes place when the enabling signal is finally generated.

Arbitration apparatus for determining priority of access to a shared bus

Growing community of inventors

Vestal, NY, United States of America

Carl A Malmquist