Beken Corporation

Caogang Yu

Weifeng Wang

Dawei Guo

Pengfei Zhang

Ronghui Kong

Yiming Huang

Zhifu Liu

Zhilei Wang

Lizhen Zhu

Pujie Yang

Zhengheng Zhou

A fetch process for a computing system is described herein. The computing system comprises a non-transitory memory. In the non-transitory memory, instructions are stored in Cycle-Redundancy Blocks (CRC blocks). Each of these CRC blocks comprises a first CRC code associated with the instructions stored in the CRC block. During a fetch process, the computing system generates a second CRC code based on the instructions stored in the CRC block and compares the second CRC code with the first CRC code to ascertain the success of the fetch process.

Systems and methods for fetching and writing instructions to memory

A system for recovering pairing information of wireless devices is provided. The system may include a first device (such as a mouse) and a second device (such as a dongle) that are wirelessly paired. The system can determine a pairing information damage in one of the first device and the second device, and can automatically recover the pairing information without even noticed by the user. In this way, the system can be less affected by the pairing information damage, and can have extended product life and improved customer experience.

System and method of recovering pairing information of wireless devices

A receiver comprises an I/Q demodulator generates an angular signal by demodulating an in-phase branch and a quadrature branch of a received signal; a filter communicatively coupled to the I/Q demodulator and configured to generate a filtered angular signal by filtering out a noise signal having a frequency higher than a predetermined frequency value from the angular signal; an angle subtractor communicatively coupled to the filter and configured to generate a phase signal based on the filtered angular signal; a phase calibrator communicatively coupled to the angle subtractor and configured to generate a calibrated phase signal based on at least one received preamble signal corresponding to the phase signal and a known value of the at least one received preamble signal corresponding to the phase signal; and a symbol decider communicatively coupled to the phase calibrator and configured to generate an output symbol based on the calibrated phase signal.

Receiver and method for calibrating frequency offset

A fractional-N frequency synthesizer comprising a multi-phase generator, a multi-path error phase generator; a current combiner; a loop filter connected to the current combiner; an oscillator () connected to the loop filter; a frequency divider (); a SDM connected to both the frequency divider and the multi-phase generator, to generate variable division ratio.

Fractional-N frequency synthesizer and method thereof

A switching unit comprises a COordinate Rotation DIgital Computer (CORDIC) unit configured to estimate a maximum phase difference between a phase of the GFSK modulated signal to be switched and a phase of the QPSK modulated signal after switch; a timing unit communicatively coupled to the CORDIC unit and configured to generate adaptive steps according to a switch time and the estimated maximum phase difference, wherein the CORDIC is further configured to generated an adjusted GFSK modulated signal by adjusting a phase of the GFSK modulated signal to be switched according to the estimated maximum phase difference and the adaptive steps.

Transmitter for transmitting packets and method thereof

A circuit for compensating quantized noise in fractional-N frequency synthesizer, comprising a PLL circuit that locks a phase compensated signal to a phase of a reference phase, wherein the phase lock loop circuit comprises a frequency divider and a phase frequency detector; a sigma-delta modulation and phase difference calculator coupled to the frequency divider generating an accumulated phase error by accumulating all previous differences between an input of the frequency divider and an output of the frequency divider within a period; a digital controlled delay line coupled to both the frequency divider and the SDM and Phase Difference calculator and generates the phase compensated signal by multiplying the accumulated phase error with a delay control word; and the phase frequency detector further generates a phase error by comparing the phase compensated signal with the reference clock.

Circuit and method for compensating noise

A method and system to reduce the noise floor of a communications system is disclosed. The system may be incorporated into any device that provides binary samples from a datastream, such as a cordless telephone system. The system is configured to determine a number of bits of the binary samples that are affected by noise. The system is then able to remove the noise by setting those bits to a fixed value. The fixed value may depend on whether the sample is positive or negative. The value to set may be chosen so that the least significant bits of each sample come as close as possible to 0 for that particular numerical representation system. The system can be integrated with other known signal processing methods.

Low cost noise floor reduction

A GFSK modulator comprises: a first compensation module, configured to receive a GFSK pulse signal, apply a first amplitude compensation and a first delay compensation to the GFSK pulse signal, so as to generate a first compensated control signal; a second compensation module, configured to receive the GFSK pulse signal, apply a second amplitude compensation and a second delay compensation to the GFSK pulse signal, so as to generate a second compensated control signal; a closed-loop PLL module including a closed-loop PLL, configured to receive and use the first and the second compensated control signals to generate a modulated signal.

GFSK modulator and a method for reducing residual frequency modulation and a digital enhanced cordless telecommunication transmitter including the GFSK modulator

When there are unused data slots available, a system allocates redundant slots in a data frame to a single mobile unit. A receiving device calculates a quality of slot (QoS) score for each slot that it receives data for. After the QoS score is calculated, the system calculates a Quality of Audio Segment (QoAS) score for each individual segment. It does so by comparing the individual audio segments that were received. Segments that are identical are assigned a positive score, while segments that differ get no score. The QoAS for each segment is added to the QoS for the slot the segment was transmitted in to generate the total score. The system then chooses the segment with the highest total score. If the total score is above a specified threshold, the system outputs the segment to the next component. Otherwise, it outputs a mute segment.

Apparatus and method for error concealment for a digital wireless phone

An apparatus to enable half-duplexing capabilities in a two-way communication device is disclosed. The apparatus estimates the signal power and background noise of a first input signal and a second input signal during approximately the same period. The apparatus further provides at least one control signal based on the result of one or more determinations. These determinations may include whether the estimated signal power of at least one of the first and second input signals exceeds a threshold value; whether the estimated signal power of the first input signal exceeds the sum of a first threshold value and the estimated background noise of the first input signal; and whether the estimated signal power of the second input signal exceeds the sum of a second threshold value and the estimated background noise of the second input signal. Other embodiments for use with two-way communication devices and related methods are also disclosed.

Systems and methods for half-duplex speakerphones and other two-way communication devices

A method, system, and apparatus for squelching a signal in telecommunications systems. The apparatus includes a filter, two power detectors, a divider, two comparators, a logic gate, and a gain control block. The apparatus receives an input signal, and the power of the signal is detected. The input signal is also filtered to pass only the noise portion of the signal, and the power of the filtered signal is detected. A ratio between the filtered signal power and the input signal power is determined. A first comparator receives the filtered signal power and a second comparator receives the ratio of the filtered signal power and the input signal power. The logic gate receives the outputs from the first and second comparators. The gain control block receives as inputs the logic gate's output and the input signal to the apparatus. The gain control block may attenuate the input signal based on the logic gate's output. The gain control block generates the output signal of the apparatus.

Integrated squelch circuit with programmable engagement threshold

A method and apparatus for automatic frequency correction in a demodulation circuit. The apparatus includes a demodulator, a frequency offset estimator, a frequency controller, and an oscillator. The oscillator provides a receiver clock signal which the demodulator employs to demodulate a modulated signal. The frequency offset estimator estimates an offset between a carrier wave frequency of the modulated signal and a frequency of the receiver clock signal. The frequency controller provides a frequency control signal to the oscillator for adjusting the frequency of the receiver clock. While the estimated offset is outside of an adjustment range, the frequency controller maintains the frequency control signal at its previous value. The frequency controller also adjusts the adjustment range based on past error signal values.

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Shanghai, China

Caogang Yu