Marvell International Limited

Marvellworld Trade Ltd.

Cao-Thong Tu

David Cousinard

Lydi Smaini

Miljan Vuletic

Patrick Clement

Olivier Burg

Frederic Declercq

Randy Tsang

Xiang Gao

Heinz Bernhard Maeder

Michel Moser

Konstantinos Manetakis

Philippe Mosch

Embodiments described herein provide circuitry employing an inductor having enhanced circuit area usage. The circuitry includes an inductor having a first loop and a second loop adjoining the first loop to form a figure-eight configuration. The circuitry further includes a circuit component disposed at least partially inside an area defined by at least one of the first loop and the second loop. The inductor has an intersection portion between the first loop and the second loop. An input node is located proximate to the intersection portion, the input node having a first extension disposed inside the first loop. An output node is located proximate to the intersection portion. The output node has a second extension disposed inside the second loop. At least a first capacitor is coupled to the input node and the second extension, and at least a second capacitor coupled to the output node and the first extension.

Systems and methods for an inductor structure with enhanced area usage of a circuit

A method of adjusting signal processing in a receiver based on signal strength includes determining a received signal strength indicator (RSSI) level, defining an RSSI value to be high when the RSSI level is above a first threshold or defining the RSSI value to be low when the RSSI level is below the first threshold, determining an automatic gain control (AGC) gain level, defining an AGC value to be high when the AGC gain level is above a second threshold or defining the AGC value to be low when the AGC gain level is below the second threshold, and adjusting power consumption of one or more receiver stages based on the RSSI value and the AGC value.

Receiver dynamic power management

Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.

Methods and devices for multiple-mode radio frequency synthesizers

In one embodiment the present invention includes a method of generating an oscillating signal at different frequencies. The method comprises configuring a digitally controlled oscillator (DCO). The DCO is configured to generate the oscillating signal at a first frequency, and the DCO is configured to generate the oscillating signal at a second frequency. Additionally, the DCO is configured to transition from the first frequency to the second frequency during a transition time period. During the transition time period, the DCO activates the second frequency and deactivates the first frequency during a plurality of time intervals. The time intervals for activating the second frequency and deactivating the first frequency successively increase from the beginning of the transition time period to the end of the transition time period.

Circuit and method for adjusting a digitally controlled oscillator

A system includes a weighting module, a mixer module, and a frequency selective impedance (FSI). The weighting module is configured to receive an input signal having an amplitude and to generate weighted outputs. Amplitudes of the weighted outputs have ratios relative to the amplitude of the input signal. The mixer module has switches configured to receive the weighted outputs and to generate a staircase waveform when the switches are clocked by clock signals. Amplitudes of steps of the staircase waveform are based on the ratios. The FSI is configured to communicate with the switches. The switches are configured to translate an impedance of the FSI centered on a first frequency to a second frequency determined by a frequency of the clock signals.

Harmonic-reject FTI filter

A controller in a receiver monitors RSSI and AGC gain levels to determine signal conditions and adjust filter performance accordingly to optimize power consumption while providing acceptable signal quality. When RSSI level is high and AGC gain is low, a strong signal-of-interest is present. In this case, adaptive filter bias currents may be reduced raise the noise floor and degrade intermodulation to reduce power consumption because the strong signal-of-interest can tolerate the higher noise and distortion. When the RSSI level is low and AGC gain is high, a weak signal is present a low noise mode may be effected by increasing bias current to filters used to lower the noise floor, but intermodulation effects may still be tolerated so those filters may be cut back. Other cases are supported. RSSI and AGC gain level thresholds may be dynamically altered based on relative RSSI and AGC levels.

In one embodiment, the present invention includes noise reduction circuits and methods. In one embodiment, cross coupled switching transistors incorporate bias voltages between the control terminal of each transistor and the drain of the other transistor. The bias voltages increase the voltage on each transistors drain terminal and reduce noise upconversion in the system. In one embodiment, the source voltages of each transistor may be increased to linearize the circuit and further reduce noise. In another embodiment, a current is coupled to a PN junction to generate a low noise bias voltage. The bias voltage is used to bias capacitors of a selectively activated and deactivated capacitance to reduce noise. Features and advantages of the present invention may be implemented in an oscillator circuit, which may be used in a communication system, for example.

Bias circuit to reduce flicker noise in tunable LC oscillators

A polyphase filter comprises an impedance network. The polyphase filter also comprises a first differential amplifier that includes first inverting and non-inverting inputs and first inverting and non-inverting outputs. The first inverting and non-inverting inputs communicate through the impedance network with a first phase and a shifted first phase of an input signal, respectively. A second differential amplifier of the polyphase filter includes second inverting and non-inverting inputs and second inverting and non-inverting outputs. The second inverting and non-inverting inputs communicate with a second phase and a shifted second phase of the input signal, respectively, through the impedance network. The second phase is offset from the first phase.

Polyphase filter having a tunable notch for image rejection

Circuits and methods for frequency modulation (FM) using a digital frequency-locked loop (DFLL). A digitally controlled oscillator (DCO) generates and adjusts a frequency of a modulated signal based on a digital tuning word. A DFLL control logic circuit receives a feedback of the modulated signal and generates a carrier signal word. A sigma delta modulator circuit receives an input signal and applies dithering to produce a dithered input signal word. An adder circuit receives and sums the dithered input signal word and the carrier signal word to produce the digital tuning word. The DFLL control logic circuit adjusts the carrier signal word to lock a carrier frequency of the modulated signal.

Frequency modulation using a digital frequency locked loop

A body switch system includes a timing module that generates a plurality of clock signals, an input node that receives an input signal, an output node that transmits an output signal; and a body switch circuit that selectively couples a body of a first transistor of a plurality of transistors to one of the input node and the output node and a body of a second transistor of the plurality of transistors to the other one of the input node and the output node based on the plurality of clock signals.

Enhanced transmission gate

A hybrid sigma-delta converter that includes a continuous-time circuit that processes an input signal and generates a first output signal, an interface circuit that receives the first output signal from the continuous-time circuit and filters the first output signal thereby generating a second output signal, and a discrete-time circuit that processes the second output signal received from the interface circuit. The interface circuit further reduces the coupling of noise generated from the operation of the discrete time circuit to the preceding continuous-time circuit.

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Preverenges, Switzerland

Cao-Thong Tu